pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 230

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

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12.0 The Internal Clock
12.1 THE CLOCK SOURCE
The source of the internal clock of the PC87317VUL can be
24 MHz or 48 MHz clock signals via the X1 pin, or an inter-
nal on-chip clock multiplier fed by the 32.768 KHz crystal of
the Real-Time Clock (RTC). The clock source is determined
by bits 1,0 of the Power Management Control 2 (PMC2) reg-
ister of logical device 8. See Section 10.2.6 "Power Man-
agement Control 2 Register (PMC2)" on page 221. Bit 0 is
determined by the CFG0 strap pin. Toggling of the 32.768
KHz clock cannot be stopped while V
the 32.768 KHz oscillator is not running, the internal circuit
is blocked.
12.2 THE INTERNAL ON-CHIP CLOCK MULTIPLIER
Two events can trigger the internal on-chip clock multiplier.
One is power-on while V
the multiplier enable bit (bit 2 of the PMC2 register of logical
device 8) from 0 to 1. See Section10.2.6 "Power Manage-
ment Control 2 Register (PMC2)" on page 221. This bit can
also disable the clock multiplier and its output clock.
Once enabled, the output clock of the clock multiplier is fro-
zen until the clock multiplier can provide an output clock that
meets all requirements; then it starts. When the power is
turned on, the PC87317VUL wakes up with the internal on-
chip clock multiplier disabled.
The 32.768 KHz and output clocks of the internal on-chip
clock multiplier operate regardless of the status of the Mas-
ter Reset (MR) signal. They can operate while MR is active.
The multiplier must have a 32.768 KHz input clock operat-
ing. Otherwise, the multiplier waits until this input clock
starts operating.
Bit 7 of the PMC2 register of logical device 8 is the Valid
Multiplier Clock status bit. When the 32.768 KHz clock tog-
gles before MR becomes active, this bit is usually set to 1
before power-up reset ends (while MR is high, if MR is high
for a few msec).
While it is stabilizing, the output clock is frozen and the sta-
tus bit is cleared to 0 to indicate a frozen clock. When the
clock multiplier becomes stable, the output clock starts tog-
gling and the status bit is set to 1. A longer time is required
to set the Valid Multiplier Clock status bit if the multiplier
waits for a stable 32.768 KHz clock.
The Valid Multiplier Clock status bit indicates when the
clock is operating. Software should poll this bit and activate
(enable) the KBC, FDC, UART1, the UART2 and infrared in-
terface (IR), and the Parallel Port according to its value.
The multiplier and its output clock do not use power when
they are disabled.
12.3 SPECIFICATIONS
Wake-up time (from the time the 32.768 KHz clock is op-
erating and on-chip clock multiplier is enabled) is a max-
imum of 1.5 msec.
Tolerance (long term deviation) of the multiplier output
clock, above the 32.768 KHz tolerance, is
Total tolerance is therefore
ance + 110 ppm).
Cycle by cycle variance is a maximum of 0.1 nsec.
Power consumption is a maximum of 5 mA.
DD
is active. The other is changing
(32.768 KHz clock toler-
CCH
is active. When
110 ppm.
The Internal Clock
230
12.4 POWER-ON PROCEDURE WHEN CFG0 = 0
For proper operation, follow the procedure below after pow-
er-on:
1. If on-chip clock multiplier is used: Go to step 2.
2. Set bit 2 of PMC2 register of logical device 8 to 1. The
3. Poll bit 7 of PMC2 register of logical device 8. Wait until
4. Enable any module of the PC87317.
If 24 MHz or 48 Mhz clock on X1 pin is used: Set bits 0
and 1 of PMC2 register of logical device 8 to the desired
clock source. Go to step 4.
on-chip clock multiplier is enabled and starts stabilizing.
Steps 1 and 2 can be unified, if both are required.
it is set to 1. When set to 1, go to step 4.