pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 56

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

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Oscillator Activity
The RTC internal oscillator circuit is active whenever power
is supplied to the RTC with the following exceptions:
These conditions disables the oscillator.
When the oscillator becomes inactive, the APC is disabled.
4.1.4
The RTC logic device has a single Interrupt Request line,
IRQ, which handles three interrupt conditions. The Periodic,
Alarm, and Update-Ended interrupts are generated (IRQ is
driven low) if the respective enable bits in Control Register
B are set when an interrupt event occurs.
Reading RTC Control Register C (CRC) clears all interrupt
flags. Thus, it is recommended that when multiple interrupts
are enabled, the interrupt service routine should first read
and store the CRC register, then deal with all pending inter-
rupts by referring to this stored status.
If an interrupt is not serviced before a second occurrence of
the same interrupt condition, the second interrupt event is
lost. FIGURE 4-5 "Interrupt/Status Timing" on page 57 illus-
trates interrupt and status timing in the PC87317VUL.
4.2 THE RTC REGISTERS
The RTC registers can be accessed at any time during non-
battery backed operation. The registers are listed in TABLE
4-1 "RTC Control Registers" on page 53 and described in
detail in the sections that follow.
The RTC registers and the RAM cannot be written to before
reading the VRT bit (bit 7 of the Section 4.2.4 "RTC Control
Register D (CRD)" on page 58), thus preventing bank selec-
tion and other functions. The user must read the VRT bit as
part of the startup activity in order to be able to access the
RTC/APC registers.
For registers with reserved bits, the “Read-Modify-Write”
technique should be used.
When battery voltage is below 1 volt and MR is 1, all in-
put signals are enabled immediately upon detection of
system voltage above that of battery voltage. This also
initializes registers at indexes 00h through 0Dh.
If the VRT bit (bit 7 in Control Register D) is 0, all input
signals are enabled immediately upon detection of sys-
tem voltage above that of battery voltage.
trol bits (DV2-0), i.e., bits 6-4, of Control Register A,
and the RTC is supplied by V
The RTC is supplied by V
trol Register D is 0.
Software wrote 000 or 001 to the Divider Chain Con-
Interrupt Handling
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
BAT
BAT,
and the VRT bit of Con-
or
56
4.2.1
The CRA register controls periodic interrupt rate selection
and bank selection.
Bits 3-0 - Periodic Interrupt Rate Select (RS3-0)
Bits 6-4 - Divider Chain Control (DV2-0)
7
0
These read/write bits select one of fifteen output taps
from the clock divider chain to control the rate of the peri-
odic interrupt. See TABLE 4-2 "Periodic Interrupt Rate
Encoding" below and FIGURE 4-5 "Interrupt/Status Tim-
ing" on page 57.
Master reset does not affect these bits.
These read/write bits control the configuration of the di-
vider chain for timing generation and memory bank se-
lection, as shown in TABLE 4-3 "Divider Chain Control
and Bank Selection" on page 57.
Master reset does not affect these bits.
TABLE 4-2. Periodic Interrupt Rate Encoding
6
0
UIP
3 2 1 0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
RS3-0
RTC Control Register A (CRA)
5
DV2
1
DV1
4
0
DV0
3
0
RS3
2
0
RS2
1
0
Periodic Interrupt Rate
RS1
0
0
1.953125
3.90625
122.070
244.141
488.281
976.562
3.90625
7.8125
7.8125
15.625
31.25
Power-Up
Reset
Required
none
62.5
RS0
125
250
500
RTC Control
Register A
Index 0Ah
msec
msec
msec
msec
msec
msec
msec
msec
msec
msec
msec
sec
sec
sec
sec
(CRA)