pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 225

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

10.2.19 ACPI Support Register
This register allows the system to enter suspended mode
via software emulation. It also supports the Global Lock
mechanism.
Upon reset, this register is initialized to 00h.
Bit 0 - Sleep Enable Status
This sticky bit shows the status of the Sleep Enable bit
Bit 1 - Enable POR on Sleep Enable
Bit 2 - ACPI Global Lock Status
FIGURE 10-18. General Purpose Base Address Bits
0
0
7
7
It is set to “1” when the Sleep Enable bit (in the
PM1_CNT_HIGH register in the fixed ACPI registers,
Logical device 7) is written with a “1”. It is cleared to “0”
only when software writes a “1” to it.
This bit is enables activation of the POR interrupt re-
quest pin, when the Sleep Enable Status bit goes to 1.
0: Sleep Enable Status bit is ignored.
1: Activate POR pin if Sleep Enable Status is “1”.
This sticky bit is set to “1” when a “1” is written to the
ACPI Global Lock release bit (bit 2 in the ACPI fixed reg-
ister PM1_CNT_LOW). It is cleared to “0” only when
software writes a “1” to it.
FIGURE 10-19. ACPI Support Register Bitmap
0
0
6
6
0
0
5
5
Reserved
0
0
4
4
General Purpose Status Base Address
BIOS Global Lock release
0
0
3
3
15-8 Register Bitmap
Base Address Bits 15-8
General Purpose Status
ACPI GLobal Lock Enable
0
0
2
2
ACPI GLobal Lock Status
0
0
1
1
Enable POR on Sleep Enable
0
0
0
0
Reset
Required
Reset
Required
Sleep Enable Status
Register Bits 15-8,
Power Management (Logical Device 8)
ACPI Support
Index 10h
Index 0Fh
Register
225
Bit 3 - ACPI Global Lock Enable
Bit 4 - BIOS Global Lock Release
Bit 5 - SMI Command Status
Bit 6 - SMI Command Enable
Bit 7 - Mask PM1 Event Register Bits
0: ACPI GLobal Lock Status bit is ignored (bit 2 of this
1: Activate POR pin if Sleep Enable Status is “1.
When “1” is written to this bit, the GLobal Lock Status bit
is set to “1” (fixed ACPI register PM1_STS_LOW, bit 5),
and as SCI interrupt request can be thus asserted.
Writing a “0” to this bit has no effect on the SCI signal.
This is a sticky bit. It is set to '1', when SMI Command
Register is written (see ACPI Fixed registers). It is
cleared to '0' only by software writing a one.
0: SMI Command Status bit is ignored (bit 5 of the
1: Activate the POR pin, when the SMI Command
0: All defined bits of PM1 Event Registers are func-
1: Only RTC_STS, RTC_EN and WAK_STS bits of
This bit does not effect TMR_STS and TMR_EN bits
which behave according to bit 0 of PMC3 register.
register).
ACPI Support register).
Status bit is '1'.
tional.
PM1 Event Registers are functional. All other de-
fined bits are forced to ‘0’ (writes to these ‘other de-
fined’ bits are ignored).
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