pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 73

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

Bit 5 - RAM Block Write
Bit 6 - RAM Mask Write
Bit 7 - RAM Lock
4.5.9
This register contains the Wake up Century settings.
Bits 5-0 Wake up Century Bits
01 to 99 in BCD format or 01 to 63 in Binary format. See
“Predetermined Wake-Up” on page 68.
Bits 7,6 - Don’t Care control bits
When both bits are set to 11, these bits set the Wake up
Century field to a “don’t care” state
4.5.10 APC Control Register 3 (APCR3)
This register defines device I/O pin designations, and
GPIO10 event polarity/edge settings.
This register in not affected by Master reset. Upon first Pow-
er-Up, it is initialized to A0h.
7
1
This bit controls writes to bytes 80h-9Fh (00h-1Fh of up-
per RAM).
0: This bit has no effect on upper RAM access.
1: Writes to bytes 00h-1Fh of upper RAM are ignored.
This bit controls writes to all RTC RAM.
0: This bit has no effect on RAM access.
1: Writes to bank 0 RAM and to upper RAM are ig-
0: This bit has no effect on RAM access.
1: Read and write to locations 38h-3Fh of all banks
These bits contain the Century setting. Values may be
6
1
nored.
are blocked. Writes are ignored, and reads return
FFh.
“Don’t Care” control bits
Wake up Century Register (WCR)
FIGURE 4-22. WCR Register Bitmap
5
0
4
0
3
0
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
2
0
Wake up Century Bits
1
0
0
0
Power-Up
Reset
Required
Wake up Century
Index 48h
Register
Bank 2
(WCR)
73
Bit 0 - PME1 or GPIO16 Pin Select
Bit 1 - PME2 or GPIO15 pin select
Bit 2 - LED or CS0 Pin select
Bit 3 - GPIO24 or IRRX1 Pin Select
Bit 4 - GPIO37 or IRRX2/IRSL0/ID0 Pin Select
Bits 7-5 - GPIO10 Event Polarity/Edge Select
1
7
This bit selects PME1 or GPIO16 to be connected to I/O
pin.
When PME1 is not selected, its enable bit (bit 0 of
GP1_EN) should be cleared to 0.
0: GPIO16 selected.
1: PME1 selected.
This bit selects PME2 or GPIO15 to be connected to I/O
pin.
When PME2 is not selected, its enable bit (bit 1 of
GP1_EN) should be cleared to 0.
0: GPIO15 selected.
1: PME2 selected.
This bit selects LED or CS0 to be connected to I/O pin.
0: CS0 selected.
1: LED selected.
This bit selects GPIO24 or IRRX1 to be connected to I/O
pin.
When IRRX1 is not selected, its enable bit (bit 2 of
GP1_EN) must be cleared to 0.
0: IRRX1 selected.
1: GPIO24 selected.
This bit selects GPIO37 or IRRX2/IRSL0/ID0 to be con-
nected to I/O pin. Selection between IRRX2/IRSL0/ID0
is described in the UART2 registers (device 5).
When IRRX2 is not selected, its enable bit must be
cleared to 0.
0: IRRX2/IRSL0/ID0 selected.
1: GPIO37 selected.
These bits determine the physical conditions that trig-
6
0
ger the GPIO10 General Purpose Event.
FIGURE 4-23. APCR3 Register Bitmap
5
1
GPIO10 Event Polarity/Edge select
4
0
GPIO37 or IRRX2/IRSL0/ID0 Select
0
3
GPIO24 or IRRX1 select
0
2
0
1
LED or CS0 select
0
PME2 or GPIO15 select
0
Power-Up
Reset
Required
PME1 or GPIO16 select
APC Control
Register 3
Index 49h
www.national.com
(APCR3)
Bank 2,