pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 165

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

the stream of samples can be used to reconstruct the in-
coming bit string. To obtain good resolution, a fairly high
sampling rate should be selected.
The “Programmed-T-Period” mode should be used with the
receiver demodulator enabled. The T Period represents
one half bit time for protocols using biphase encoding, or
the basic unit of pulse distance for protocols using pulse dis-
tance encoding. The baud is usually programmed to match
the T Period. For long periods of logic low or high, the re-
ceiver samples the demodulated signal at the programmed
sampling rate.
Whenever a new infrared energy pulse is detected, the re-
ceiver synchronizes the sampling process to the incoming
signal timing. This reduces timing related errors and elimi-
nates the possibility of missing short infrared pulse se-
quences, especially with the RECS 80 protocol.
In addition, the “Programmed-T-Period” sampling minimiz-
es the amount of data used to represent the incoming infra-
red signal, therefore reducing the processing overhead in
the host CPU.
7.8 FIFO TIME-OUTS
Time-out mechanisms prevent received data from remain-
ing in the RX_FIFO indefinitely, if the programmed interrupt
or DMA thresholds are not reached.
An RX_FIFO time-out generates a Receiver Data Ready in-
terrupt and/or a receiver DMA request if bit 0 of IER and/or
bit 2 of MCR (in Extended mode) are set to 1 respectively.
An RX_FIFO time-out also sets bit 0 of ASCR to 1 if the
RX_FIFO is below the threshold. When a Receiver Data
Ready interrupt occurs, this bit is tested by the software to
determine whether a number of bytes indicated by the
RX_FIFO threshold can be read without checking bit 0 of
the LSR register.
The conditions that must exist for a time-out to occur in the
various modes of operation are described below.
When a time-out has occurred, it can only be reset when the
FIFO is read by the CPU or DMA controller.
7.8.1
Two timers (timer1 and timer 2) are used to generate two
different time-out events (A and B, respectively). Timer 1
times out after 64 sec. Timer 2 times out after four charac-
ter times.
Time-out event A generates an interrupt and sets the
RXF_TOUT bit (bit 0 of ASCR) when all of the following are
true:
Time-out event B activates the receiver DMA request and is
invisible to the software. It occurs when all of the following
are true:
At least one byte is in the RX_FIFO, and
More than 64 sec or four character times, whichever is
greater, have elapsed since the last byte was loaded
into the RX_FIFO from the receiver logic, and
More than 64 sec or four character times, whichever is
greater, have elapsed since the last byte was read from
the RX_FIFO by the CPU or DMA controller.
At least one byte is in the RX_FIFO, and
More than 64 sec or four character times, whichever is
smaller, have elapsed since the last byte was loaded
into the RX_FIFO from the receiver logic, and
UART, SIR or Sharp-IR Mode Time-Out Conditions
Enhanced Serial Port with IR - UART2 (Logical Device 5)
165
7.8.2
The RX_FIFO time-out, in Consumer-IR mode, is disabled
while the receiver is active. It occurs when all of the follow-
ing are true:
7.8.3
This feature allows software to send high-speed data in Pro-
grammed Input/Output (PIO) mode without the risk of gen-
erating a transmitter underrun.
Transmission deferral is available only in Extended mode
and when the TX_FIFO is enabled. When transmission de-
ferral is enabled (TX_DFR bit in the MCR register set to 1)
and the transmitter becomes empty, an internal flag is set
and locks the transmitter. If the CPU now writes data into
the TX_FIFO, the transmitter does not start sending the
data until the TX_FIFO level reaches 14 at which time the
internal flag is cleared. The internal flag is also cleared and
the transmitter starts transmitting when a time-out condition
is reached. This prevents some bytes from being in the
TX_FIFO indefinitely if the threshold is not reached.
The time-out mechanism is implemented by a timer that is
enabled when the internal flag is set and there is at least
one byte in the TX_FIFO. Whenever a byte is loaded into
the TX_FIFO the timer gets reloaded with the initial value. If
no bytes are loaded for a 64- sec time, the timer times out
and the internal flag is cleared, thus enabling the transmit-
ter.
7.9 AUTOMATIC FALLBACK TO A NON-EXTENDED
The automatic fallback feature supports existing legacy
software packages that use the 16550 UART by automati-
cally turning off any Extended mode features and switches
the UART to Non-Extended mode when either of the LB-
GD(L) or LBGD(H) ports in bank 1 is read from or written to
by the CPU.
This eliminates the need for user intervention prior to run-
ning a legacy program.
In order to avoid spurious fallbacks, alternate baud registers
are provided in bank 2. Any program designed to take ad-
vantage of the UART’s extended features, should not use
LBGD(L) and LBGD(H) to change the baud. It should use
the BGD(L) and BGD(H) registers instead. Access to these
ports will not cause fallback.
More than 64 sec or four character times, whichever is
smaller, have elapsed since the last byte was read from
the RX_FIFO by the CPU or DMA controller.
At least one byte has been in the RX_FIFO for 64 sec
or more, and
The receiver has been inactive (RXACT = 0) for 64 sec
or more, and
More than 64 sec have elapsed since the last byte was
read from the RX_FIFO by the CPU or DMA controller.
UART MODE
Consumer-IR Mode Time-Out Conditions
Transmission Deferral
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