xq2vp40 Xilinx Corp., xq2vp40 Datasheet - Page 13

• Manufacturer Part Number: xq2vp40
• Description: Qpro Virtex-ii Pro 1.5v Platform Fpgas Complete Data Sheet
• Manufacturer: Xilinx Corp.

Functional Features
Common Features
•
•
•
•
•
•
•
Data-Side OCM (DSOCM)
•
•
•
•
•
•
Instruction-Side OCM (ISOCM)
The ISOCM interface contains a 64-bit read only port, for
instruction fetches, and a 32-bit write only port, to initialize
or test the ISBRAM. When implementing the read only port,
the user must deassert the write port inputs. The preferred
method of initializing the ISBRAM is through the
configuration bitstream.
•
•
•
•
•
•
DS136-2 (v2.0) December 20, 2007
Preliminary Product Specification
Separate Instruction and Data memory interface
between processor core and BRAMs in FPGA
Dedicated interface to Device Control Register (DCR)
bus for ISOCM and DSOCM
Single-cycle and multi-cycle mode option for I-side and
D-side interfaces
Single cycle = one CPU clock cycle;
multi-cycle = minimum of two and maximum of eight
CPU clock cycles
FPGA configurable DCR addresses within DSOCM
and ISOCM.
Independent 16 MB logical memory space available
within PPC405 memory map for each of the DSOCM
and ISOCM. The number of block RAMs in the device
might limit the maximum amount of OCM supported.
Maximum of 64K and 128K bytes addressable from
DSOCM and ISOCM interfaces, respectively, using
address outputs from OCM directly without additional
decoding logic.
32-bit Data Read bus and 32-bit Data Write bus
Byte write access to DSBRAM support
Second port of dual port DSBRAM is available to
read/write from an FPGA interface
22-bit address to DSBRAM port
8-bit DCR Registers: DSCNTL, DSARC
Three alternatives to write into DSBRAM: BRAM
initialization, CPU, FPGA H/W using second port
64-bit Data Read Only bus (two instructions per cycle)
32-bit Data Write Only bus (through DCR)
Separate 21-bit address to ISBRAM
8-bit DCR Registers: ISCNTL, ISARC
32-bit DCR Registers: ISINIT, ISFILL
Two alternatives to write into ISBRAM: BRAM
initialization, DCR and write instruction
R
www.xilinx.com
Clock/Control Interface Logic
The clock/control interface logic provides proper
initialization and connections for PPC405 clock/power
management, resets, PLB cycle control, and OCM
interfaces. It also couples user signals between the FPGA
fabric and the embedded PPC405 CPU core.
The processor clock connectivity is similar to CLB clock
pins. It can connect either to global clock nets or general
routing resources. Therefore the processor clock source
can come from DCM, CLB, or user package pin.
CPU-FPGA Interfaces
All Processor Block user pins link up with the general FPGA
routing resources through the CPU-FPGA interface. Therefore
processor signals have the same routability as other non-
Processor Block user signals. Longlines and hex lines travel
across the Processor Block both vertically and horizontally,
allowing signals to route through the Processor Block.
Processor Local Bus (PLB) Interfaces
The PPC405 core accesses high-speed system resources
through PLB interfaces on the instruction and data cache
controllers. The PLB interfaces provide separate 32-bit
address/64-bit data buses for the instruction and data sides.
The cache controllers are both PLB masters. PLB arbiters
are implemented in the FPGA fabric and are available as
soft IP cores.
Device Control Register (DCR) Bus Interface
The device control register (DCR) bus has 10 bits of
address space for components external to the PPC405
core. Using the DCR bus to manage status and
configuration registers reduces PLB traffic and improves
system integrity. System resources on the DCR bus are
protected or isolated from wayward code since the DCR bus
is not part of the system memory map.
External Interrupt Controller (EIC) Interface
Two level-sensitive user interrupt pins (critical and non-
critical) are available. They can be either driven by user
defined logic or Xilinx soft interrupt controller IP core
outside the Processor Block.
Clock/Power Management (CPM) Interface
The CPM interface supports several methods of clock
distribution and power management. Three modes of
operation that reduce power consumption below the normal
operational level are available.
Reset Interface
There are three user reset input pins (core, chip, and
system) and three user reset output pins for different levels
of reset, if required.
Functional Description
Module 2 of 4
3