xq2vp40 Xilinx Corp., xq2vp40 Datasheet - Page 78

• Manufacturer Part Number: xq2vp40
• Description: Qpro Virtex-ii Pro 1.5v Platform Fpgas Complete Data Sheet
• Manufacturer: Xilinx Corp.

Master/Slave SelectMAP Parameters
Figure 5
Virtex-II Pro Platform FPGA User Guide.
X-Ref Target - Figure 5
Table 35: SelectMAP Mode Write Timing Characteristics
DS136-3 (v2.0) December 20, 2007
Preliminary Product Specification
CCLK
is a generic timing diagram for data loading using SelectMAP. For other data loading diagrams, refer to the
R
DATA[0:7] setup/hold
CS_B setup/hold
RDWR_B setup/hold
BUSY propagation delay
Maximum start-up frequency
Maximum frequency
Maximum frequency with no handshake
RDWR_B
DATA[0:7]
CCLK
BUSY
CS_B
Description
Figure 5: SelectMAP Mode Data Loading Sequence (Generic)
T
T
SMCCW
SMCSCC
5
T
3
SMDCC
1
No Write
7
XQ2VP40
XQ2VP70
Device
T
SMCKBY
www.xilinx.com
Write
References
2
Figure
1/2
3/4
5/6
7
T
SMCCD
No Write
T
T
T
SMCSCC
F
SMCCW
SMDCC
F
CC_SELECTMAP
CC_STARTUP
T
Symbol
F
SMCKBY
CCNH
/T
/T
/T
SMCCD
SMCCCS
SMWCC
DC and Switching Characteristics
Write
4
6
ds083-3_10_012004
5.0/0.0
6.0/0.0
7.0/0.0
7.0/0.0
T
Value
12.0
SMCCCS
T
50
50
50
SMWCC
MHz, max
MHz, max
MHz, max
Module 3 of 4
ns, max
ns, min
ns, min
ns, min
ns, min
Units
26