xq2vp40 Xilinx Corp., xq2vp40 Datasheet - Page 89

• Manufacturer Part Number: xq2vp40
• Description: Qpro Virtex-ii Pro 1.5v Platform Fpgas Complete Data Sheet
• Manufacturer: Xilinx Corp.

DS136-4 (v2.0) December 20, 2007
This document provides QPro Virtex™-II Pro Device/Package Combinations, Maximum I/Os, and QPro Virtex-II Pro Pin
Definitions, followed by pinout tables and package specifications, for the following packages:
•
•
•
For device pinout diagrams and layout guidelines, refer to the
package pinout files are also available for download from the Xilinx website (
QPro Virtex-II Pro Device/Package Combinations and Maximum I/Os
Wire-bond and flip-chip packages are available.
wire-bond and flip-chip packages, respectively.
•
•
•
Table 3
device/package combination. The number of I/Os per package includes all user I/Os except the fifteen control pins (CCLK,
DONE, M0, M1, M2, PROG_B, PWRDWN_B, TCK, TDI, TDO, TMS, HSWAP_EN, DXN, DXP, and RSVD), and the nine (per
transceiver) RocketIO™ MGT pins (TXP, TXN, RXP, RXN, AVCCAUXTX, AVCCAUXRX, VTTX, VTRX, and GNDA).
Note:
.
Table 1: Wire-Bond Packages Information
Table 3: QPro Virtex-II Pro Available User I/Os and Differential Pairs per Device/Package Combination
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DS136-4 (v2.0) December 20, 2007
Preliminary Product Specification
Pitch (mm)
Size (mm)
Maximum I/Os
"FG676 Fine-Pitch BGA Package," page 5
"EF1152, and FF1152 Flip-Chip Fine-Pitch BGA Packages," page 23
"EF1704, and FF1704 Flip-Chip Fine-Pitch BGA Packages," page 52
FG denotes wire-bond fine-pitch BGA (1.00 mm pitch).
FF denotes flip-chip fine-pitch BGA (1.00 mm pitch).
EF denotes flip-chip fine-pitch BGA with epoxy-coated chip capacitors (1.00 mm pitch).
RocketIO Multi-Gigabit Transceivers (MGTs) are not supported in QPro Virtex-II Pro FPGAs.
shows the number of available I/Os and the number of differential I/O pairs for each QPro Virtex-II Pro
XQ2VP40
XQ2VP70
Device
Package
R
9
4
Differential I/O Pairs
Differential I/O Pairs
Available User I/Os
Available User I/Os
26 x 26
FG676
1.00
412
User I/Os
Table 1
QPro Virtex-II Pro 1.5V Platform FPGAs:
www.xilinx.com
and
Table 2
UG012
Table 2: Flip-Chip Packages Information
Pitch (mm)
Size (mm)
Maximum I/Os
show the maximum number of user I/Os possible in
, Virtex-II Pro Platform FPGA User Guide. ASCII
Package
www.xilinx.com
FG676
416
202
–
–
QPro Virtex-II Pro Package
Preliminary Product Specification
Pinout Information
).
FF1152
FF1152
35 x 35
1.00
692
340
644
–
–
42.5 x 42.5
Module 4 of 4
EF1704
FF1704
EF1704
FF1704
1040
1.00
996
492
–
–
1