xq2vp40 Xilinx Corp., xq2vp40 Datasheet - Page 46

• Manufacturer Part Number: xq2vp40
• Description: Qpro Virtex-ii Pro 1.5v Platform Fpgas Complete Data Sheet
• Manufacturer: Xilinx Corp.

Specifications for M and D are provided under
Parameters"
3). By default, M = 4 and D = 1, which results in a clock
output frequency four times faster than the clock input
frequency (CLKIN).
CLK2X180 is phase shifted 180 degrees relative to CLK2X.
CLKFX180 is phase shifted 180 degrees relative to CLKFX.
All frequency synthesis outputs automatically have 50/50
duty cycles, with the exception of the CLKDV output when
performing a non-integer divide in high-frequency mode.
See
Note:
frequency mode.
Table 21: CLKDV Duty Cycle for Non-integer Divides
Phase Shifting
The DCM provides additional control over clock skew
through either coarse or fine-grained phase shifting. The
CLK0, CLK90, CLK180, and CLK270 outputs are each
phase shifted by ¼ of the input clock period relative to each
other, providing coarse phase control. Note that CLK90 and
CLK270 are not available in high-frequency mode.
Fine-phase adjustment affects all nine DCM output clocks.
When activated, the phase shift between the rising edges of
X-Ref Target - Figure 51
DS136-2 (v2.0) December 20, 2007
Preliminary Product Specification
Table 21
Note CLK2X and CLK2X180 are not available in high-
CLKDV_DIVIDE
CLKOUT_PHASE_SHIFT
= NONE
CLKOUT_PHASE_SHIFT
= FIXED
CLKOUT_PHASE_SHIFT
= VARIABLE
R
in
for more details.
1.5
2.5
3.5
4.5
5.5
6.5
7.5
"DC and Switching Characteristics" (Module
CLKIN
CLKFB
CLKIN
CLKFB
CLKIN
CLKFB
Duty Cycle
Figure 51: Fine-Phase Shifting Effects
5 / 11
6 / 13
7 / 15
3 / 7
2 / 5
4 / 9
1/ 3
"DCM Timing
(PS/256) x PERIOD CLKIN
(PS negative)
(PS/256) x PERIOD CLKIN
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(PS negative)
CLKIN and CLKFB is a specified fraction of the input clock
period.
In variable mode, the
dynamically incremented or decremented as determined by
PSINCDEC synchronously to PSCLK, when the PSEN
input is active.
shifting. For more information on DCM features, see the
Virtex-II Pro Platform FPGA User Guide.
Table 22
variable mode.
Table 22: Fine Phase Shifting Control Pins
Two separate components of the phase shift range must be
understood:
•
•
The
equation:
The full range of this attribute is always –255 to +255, but its
practical range varies with CLKIN frequency, as constrained
by the
the total delay achievable by the phase shift delay line. Total
delay is a function of the number of delay taps used in the
circuit. Across process, voltage, and temperature, this
absolute range is guaranteed to be as specified under
"DCM Timing Parameters"
Characteristics" (Module
PSINCDEC
PSEN
PSCLK
PSDONE
Control Pin
PHASE_SHIFT
FINE_SHIFT_RANGE
Phase Shift (ns) = (
PHASE_SHIFT
FINE_SHIFT_RANGE
lists fine-phase shifting control pins, when used in
(PS/256) x PERIOD CLKIN
(PS positive)
(PS/256) x PERIOD CLKIN
Figure 51
Direction
attribute range
attribute is the numerator in the following
(PS positive)
Out
PHASE_SHIFT
In
In
In
PHASE_SHIFT
illustrates the effects of fine-phase
DCM timing parameter range
3).
in
component, which represents
"DC and Switching
Increment or decrement
Active when completed
Functional Description
Enable ± phase shift
Clock for phase shift
value can also be
/256) * PERIOD
DS031_48_110300
Function
Module 2 of 4
CLKIN
36