xq2vp40 Xilinx Corp., xq2vp40 Datasheet - Page 4

• Manufacturer Part Number: xq2vp40
• Description: Qpro Virtex-ii Pro 1.5v Platform Fpgas Complete Data Sheet
• Manufacturer: Xilinx Corp.

QPro Virtex-II Pro Platform FPGA Technology
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General Description
QPro Virtex-II Pro platform FPGAs are well-suited for
designs based on IP cores and customized modules. The
family incorporates the PowerPC CPU blocks in the
Virtex-II Pro architecture. This family of FPGAs empowers
complete solutions for telecommunication, wireless,
networking, video, and DSP applications.
DS136-1 (v2.0) December 20, 2007
Preliminary Product Specification
SelectRAM+ Memory Hierarchy
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Arithmetic Functions
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Flexible Logic Resources
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High-Performance Clock Management Circuitry
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Active Interconnect Technology
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SelectIO™-Ultra Technology
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Up to 6 Mb of True Dual-Port RAM in 18 Kb block
SelectRAM+ resources
Up to 1,034 Kb of distributed SelectRAM+
resources
High-performance interfaces to external memory
Dedicated 18-bit x 18-bit multiplier blocks
Fast look-ahead carry logic chains
Up to 66,176 internal registers/latches with Clock
Enable
Up to 66,176 look-up tables (LUTs) or cascadable
variable (1 to 16 bits) shift registers
Wide multiplexers and wide-input function support
Horizontal cascade chain and Sum-of-Products
support
Internal three-state busing
Eight Digital Clock Manager (DCM) modules
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16 global clock multiplexer buffers in all parts
Fourth-generation segmented routing structure
Fast, predictable routing delay, independent of
fanout
Deep sub-micron noise immunity benefits
Up to 996 user I/Os
Twenty-two single-ended standards and
ten differential standards
Programmable LVCMOS sink/source current (2 mA
to 24 mA) per I/O
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Precise clock deskew
Flexible frequency synthesis
High-resolution phase shifting
www.xilinx.com
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The Virtex-II Pro architecture and leading-edge 0.13 µm
CMOS nine-layer copper process are optimized for high
performance designs in a wide range of densities.
Combining a wide variety of flexible features and IP cores,
the QPro Virtex-II Pro family enhances programmable logic
design capabilities and is a powerful alternative to mask-
programmed gate arrays.
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CMOS Latch-Based In-System Configuration
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Supported by Xilinx Integrated Software Environment
(ISE™) Software
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0.13 µm Nine-Layer Copper Process with 90 nm High-
Speed Transistors
1.5V (V
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IEEE 1149.1 Compatible Boundary-Scan Logic Support
Flip-Chip and Wire-Bond Ball Grid Array (BGA)
Packages in Standard 1.00 mm Pitch.
CCAUX
XCITE Digitally Controlled Impedance (DCI) I/O
PCI/ PCI-X support (refer to XAPP653, 3.3V PCI
Design Guidelines, for more information)
Differential signaling
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Proprietary high-performance SelectLink
technology for communications between Xilinx
devices
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Fast SelectMAP™ configuration
Triple Data Encryption Standard (DES) security
option (bitstream encryption)
IEEE 1532 support
Partial reconfiguration
Unlimited reprogrammability
Readback capability
Integrated VHDL and Verilog design flows
ChipScope™ Integrated Logic Analyzer
CCINT
512 Mb/s Low-Voltage Differential Signaling
I/O (LVDS) with current mode drivers
On-chip differential termination
Bus LVDS I/O
HyperTransport (LDT) I/O with current driver
buffers
Built-in DDR input and output registers
High-bandwidth data path
Double Data Rate (DDR) link
Web-based HDL generation methodology
auxiliary and V
) core power supply, dedicated 2.5V
CCO
Introduction and Overview
I/O power supplies
Module 1 of 4
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