xq2vp40 Xilinx Corp., xq2vp40 Datasheet - Page 3

• Manufacturer Part Number: xq2vp40
• Description: Qpro Virtex-ii Pro 1.5v Platform Fpgas Complete Data Sheet
• Manufacturer: Xilinx Corp.

DS136-1 (v2.0) December 20, 2007
Summary of QPro Virtex-II Pro Features
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QPro Virtex-II Pro family members and resources are shown in
Table 1: QPro Virtex-II Pro FPGA Family Members
RocketIO Transceiver Features
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PowerPC RISC Processor Block Features
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© 2006–2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. PowerPC is
a trademark of IBM Corp. and is used under license. All other trademarks are the property of their respective owners.
DS136-1 (v2.0) December 20, 2007
Preliminary Product Specification
Notes:
1.
2.
XQ2VP40
XQ2VP70
Device
Guaranteed over the full military temperature range
(–55
(–40
High-Performance Platform FPGA Solution, Including
two IBM PowerPC™ RISC processor blocks
Based on Virtex™-II Platform FPGA Technology
♦
RocketIO™ transceivers are not supported in QPro
Virtex-II Pro FPGAs.
Embedded Harvard Architecture Block
Low Power Consumption: 0.9 mW/MHz
Five-Stage Data Path Pipeline
Hardware Multiply/Divide Unit
Thirty-Two 32-bit General Purpose Registers
16 KB Two-Way Set-Associative Instruction Cache
16 KB Two-Way Set-Associative Data Cache
RocketIO™ Multi-Gigabit Transceivers (MGTs) are not supported in QPro Virtex-II Pro FPGAs.
Logic Cell ≈ (1) 4-input LUT + (1)FF + Carry Logic
Flexible logic resources
º
º
C to +125
C to +100
Transceiver
RocketIO
Blocks
8, or 12
20
º
º
C) or full industrial temperature range
C)
(1)
Processor
PowerPC
Blocks
R
2
2
8
0
43,632
74,448
Logic
Cells
(2)
CLB (1 = 4 slices =
Slices
19,392
33,088
QPro Virtex-II Pro 1.5V Platform FPGAs
max 128 bits)
www.xilinx.com
Max Distr
RAM (Kb)
1,034
606
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Table
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Memory Management Unit (MMU)
64-entry unified Translation Look-aside Buffers (TLB)
Variable page sizes (1 KB to 16 MB)
Dedicated On-Chip Memory (OCM) Interface
Supports IBM CoreConnect™ Bus Architecture
Debug and Trace Support
Timer Facilities
1.
18 X 18 Bit
CMOS latch-based in-system configuration
Active Interconnect technology
SelectRAM™+ memory hierarchy
Dedicated 18-bit x 18-bit multiplier blocks
High-performance clock management circuitry
SelectI/O™-Ultra technology
XCITE Digitally Controlled Impedance (DCI) I/O
Multiplier
Blocks
192
328
Introduction and Overview
Blocks
Block SelectRAM+
18 Kb
192
328
Preliminary Product Specification
Max Block
RAM (Kb)
3,456
5,904
DCMs
8
8
Module 1 of 4
Maximum
I/O Pads
User
692
996
1