xq2vp40 Xilinx Corp., xq2vp40 Datasheet - Page 50

• Manufacturer Part Number: xq2vp40
• Description: Qpro Virtex-ii Pro 1.5v Platform Fpgas Complete Data Sheet
• Manufacturer: Xilinx Corp.

Configuration
Virtex-II Pro devices are configured by loading application
specific configuration data into the internal configuration
memory. Configuration is carried out using a subset of the
device pins, some of which are dedicated, while others can
be re-used as general purpose inputs and outputs once
configuration is complete.
Depending on the system design, several configuration
modes are supported, selectable via mode pins. The mode
pins M2, M1, and M0 are dedicated pins. The M2, M1, and
M0 mode pins should be set at a constant DC voltage level,
either through pull-up or pull-down resistors, or tied directly
to ground or V
during and after configuration.
An additional pin, HSWAP_EN is used in conjunction with
the mode pins to select whether user I/O pins have pull-ups
during configuration. By default, HSWAP_EN is tied High
(internal pull-up) which shuts off the pull-ups on the user I/O
pins during configuration. When HSWAP_EN is tied Low,
user I/Os have pull-ups during configuration. Other
dedicated pins are CCLK (the configuration clock pin),
DONE, PROG_B, and the boundary-scan pins: TDI, TDO,
TMS, and TCK. (The TDO pin is open-drain and does not
have an internal pull-up resistor.) Depending on the
configuration mode chosen, CCLK can be an output
generated by the FPGA, or an input accepting an externally
generated clock. The configuration pins and Boundary-
Scan pins are independent of the V
supply (V
configuration pins are LVCMOS25 12mA. See
Switching Characteristics" (Module
A "persist" option is available which can be used to force the
configuration pins to retain their configuration function even
after device configuration is complete. If the persist option is
not selected then the configuration pins with the exception
of CCLK, PROG_B, and DONE can be used as user I/O in
normal operation. The persist option does not apply to the
boundary-scan related pins. The persist feature is valuable
in applications which employ partial reconfiguration or
reconfiguration on the fly.
Configuration Modes
Virtex-II Pro supports five configuration modes:
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•
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Refer to
A detailed description of configuration modes is provided in
the Virtex-II Pro Platform FPGA User Guide.
DS136-2 (v2.0) December 20, 2007
Preliminary Product Specification
"Slave-Serial Mode"
"Master-Serial Mode"
"Slave SelectMAP Mode"
"Master SelectMAP Mode"
"Boundary-Scan (JTAG, IEEE 1532) Mode"
Table 26, page
CCAUX
R
CCAUX
) of 2.5V is used for these pins. All
. The mode pins should not be toggled
41.
CCO
3).
. The auxiliary power
"DC and
www.xilinx.com
Slave-Serial Mode
In slave-serial mode, the FPGA receives configuration data
in bit-serial form from a serial PROM or other serial source
of configuration data. The CCLK pin on the FPGA is an
input in this mode. The serial bitstream must be setup at the
DIN input pin a short time before each rising edge of the
externally generated CCLK.
Multiple FPGAs can be daisy-chained for configuration from
a single source. After a particular FPGA has been
configured, the data for the next device is routed internally
to the DOUT pin. The data on the DOUT pin changes on the
falling edge of CCLK.
Slave-serial mode is selected by applying [111] to the mode
pins (M2, M1, M0). A weak pull-up on the mode pins makes
slave serial the default mode if the pins are left
unconnected.
Master-Serial Mode
In master-serial mode, the CCLK pin is an output pin. It is
the Virtex-II Pro FPGA device that drives the configuration
clock on the CCLK pin to a Xilinx Serial PROM which in turn
feeds bit-serial data to the DIN input. The FPGA accepts
this data on each rising CCLK edge. After the FPGA has
been loaded, the data for the next device in a daisy-chain is
presented on the DOUT pin after the falling CCLK edge.
The interface is identical to slave serial except that an
internal oscillator is used to generate the configuration clock
(CCLK). A wide range of frequencies can be selected for
CCLK which always starts at a slow default frequency.
Configuration bits then switch CCLK to a higher frequency
for the remainder of the configuration.
Slave SelectMAP Mode
The SelectMAP mode is the fastest configuration option.
Byte-wide data is written into the Virtex-II Pro FPGA device
with a BUSY flag controlling the flow of data. An external
data source provides a byte stream, CCLK, an active Low
Chip Select (CS_B) signal and a Write signal (RDWR_B). If
BUSY is asserted (High) by the FPGA, the data must be
held until BUSY goes Low. Data can also be read using the
SelectMAP mode. If RDWR_B is asserted, configuration
data is read out of the FPGA as part of a readback
operation.
After configuration, the pins of the SelectMAP port can be
used as additional user I/O. Alternatively, the port can be
retained to permit high-speed 8-bit readback using the
persist option.
Multiple Virtex-II Pro FPGAs can be configured using the
SelectMAP mode, and be made to start-up simultaneously.
To configure multiple devices in this way, wire the individual
CCLK, Data, RDWR_B, and BUSY pins of all the devices in
Functional Description
Module 2 of 4
40