xq2vp40 Xilinx Corp., xq2vp40 Datasheet - Page 40

• Manufacturer Part Number: xq2vp40
• Description: Qpro Virtex-ii Pro 1.5v Platform Fpgas Complete Data Sheet
• Manufacturer: Xilinx Corp.

If both ports are configured in either 2K x 9-bit, 1K x 18-bit,
or 512 x 36-bit configurations, the 18 Kb block is accessible
from port A or B. If both ports are configured in either 16K x
1-bit, 8K x 2-bit. or 4K x 4-bit configurations, the 16 K-bit
block is accessible from Port A or Port B. All other
configurations result in one port having access to an 18 Kb
memory block and the other port having access to a 16 K-bit
subset of the memory block equal to 16 Kbs. Each block
SelectRAM+ cell is a fully synchronous memory, as
illustrated in
inputs and outputs and are independently clocked.
X-Ref Target - Figure 36
Port Aspect Ratios
Table 16
18 Kb block SelectRAM+ resource. Virtex-II Pro block
SelectRAM+ also includes dedicated routing resources to
provide an efficient interface with CLBs, block SelectRAM+,
and multipliers.
Table 16: 18 Kb Block SelectRAM+ Port Aspect Ratio
Read/Write Operations
The Virtex-II Pro block SelectRAM+ read operation is fully
synchronous. An address is presented, and the read
operation is enabled by control signal ENA or ENB. Then,
depending on clock polarity, a rising or falling clock edge
causes the stored data to be loaded into output registers.
DS136-2 (v2.0) December 20, 2007
Preliminary Product Specification
Figure 36: 18 Kb Block SelectRAM+ in Dual-Port Mode
Width
18
36
1
2
4
9
shows the depth and the width aspect ratios for the
16,384
Depth
8,192
4,096
2,048
1,024
512
R
Figure
DIB
DIPA
ADDRA
WEA
ENA
SSRA
DIPB
ADDRB
WEB
ENB
SSRB
DIA
Address Bus
36. The two ports have independent
CLKA
CLKB
ADDR[13:0]
ADDR[12:0]
ADDR[11:0]
ADDR[10:0]
18-Kbit Block SelectRAM
ADDR[9:0]
ADDR[8:0]
DATA[15:0]
DATA[31:0]
Data Bus
DATA[1:0]
DATA[3:0]
DATA[7:0]
DATA[0]
DOPA
DOPB
DOA
DOB
DS031_11_102000
Parity Bus
Parity[1:0]
Parity[3:0]
Parity[0]
–
–
–
www.xilinx.com
The write operation is also fully synchronous. Data and
address are presented, and the write operation is enabled
by control signals WEA and WEB in addition to ENA or
ENB. Then, again depending on the clock input mode, a
rising or falling clock edge causes the data to be loaded into
the memory cell addressed.
A write operation performs a simultaneous read operation.
Three different options are available, selected by
configuration:
•
X-Ref Target - Figure 37
•
X-Ref Target - Figure 38
RAM Contents
RAM Contents
WRITE_FIRST
The WRITE_FIRST option is a transparent mode. The
same clock edge that writes the data input (DI) into the
memory also transfers DI into the output registers DO,
as shown in
READ_FIRST
The READ_FIRST option is a read-before-write mode.
The same clock edge that writes data input (DI) into the
memory also transfers the prior content of the memory
cell addressed into the data output registers DO, as
shown in
Data_out
Data_out
Address
Address
Data_in
Data_in
Data_in
Data_in
CLK
CLK
WE
WE
Figure 37: WRITE_FIRST Mode
Figure 38: READ_FIRST Mode
Figure
Figure
DI
DI
New
New
Old
Old
aa
aa
Internal
Internal
Memory
38.
Memory
37.
DO
DO
Functional Description
Prior stored data
Data_out = Data_in
New
New
New
Old
DS083-2_14_050901
DS083-2_13_050901
Module 2 of 4
30