xq2vp40 Xilinx Corp., xq2vp40 Datasheet - Page 22

• Manufacturer Part Number: xq2vp40
• Description: Qpro Virtex-ii Pro 1.5v Platform Fpgas Complete Data Sheet
• Manufacturer: Xilinx Corp.

Input/Output Individual Options
Each device pad has optional pull-up/pull-down resistors
and weak-keeper circuit in the LVTTL, LVCMOS, and PCI
SelectIO-Ultra configurations, as illustrated in
Values of the optional pull-up and pull-down resistors fall
within a range of 40 KΩ to 120 KΩ when V
2.38V to 2.63V only). The clamp diodes are always present,
even when power is not.
X-Ref Target - Figure 10
The optional weak-keeper circuit is connected to each user
I/O pad. When selected, the circuit monitors the voltage on
the pad and weakly drives the pin High or Low. If the pin is
connected to a multiple-source signal, the weak-keeper
holds the signal in its last state if all drivers are disabled.
Maintaining a valid logic level in this way eliminates bus
chatter. An enabled pull-up or pull-down overrides the weak-
keeper circuit.
LVCMOS25 sinks and sources current up to 24 mA. The
current is programmable (see
slew rate controls for each output driver minimize bus
Table 4: LVCMOS Programmable Currents (Sink and Source)
DS136-2 (v2.0) December 20, 2007
Preliminary Product Specification
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
SelectIO-Ultra
Figure 10: LVTTL, LVCMOS, or PCI SelectIO-Ultra
Program
Delay
R
OBUF
Program
Current
V CCO
IBUF
V CCO
2 mA
2 mA
2 mA
2 mA
2 mA
Standard
Clamp
Diode
Table
V CCO
4). Drive strength and
40KΩ –
40KΩ –
120KΩ
120KΩ
4 mA
4 mA
4 mA
4 mA
4 mA
CCO
Programmable Current (Worst-Case Guaranteed Minimum)
Keeper
Weak
V CCAUX = 2.5V
Figure
V CCINT = 1.5V
= 2.5V (from
DS083-2_07_101801
10.
6 mA
6 mA
6 mA
6 mA
6 mA
www.xilinx.com
PAD
transients. For LVDCI and LVDCI_DV2 standards, drive
strength and slew rate controls are not available.
Figure 11
configurations. HSTL can sink current up to 48 mA. (HSTL IV)
X-Ref Target - Figure 11
All pads are protected against damage from electrostatic
discharge (ESD) and from over-voltage transients.
Virtex-II Pro uses two memory cells to control the configuration
of an I/O as an input. This is to reduce the probability of an I/O
configured as an input from flipping to an output when
subjected to a single event upset (SEU) in space applications.
Prior to configuration, all outputs not involved in
configuration are forced into their high-impedance state.
The pull-down resistors and the weak-keeper circuits are
inactive. The dedicated pin HSWAP_EN controls the pull-up
resistors prior to configuration. By default, HSWAP_EN is
set High, which disables the pull-up resistors on user I/O
pins. When HSWAP_EN is set Low, the pull-up resistors are
activated on user I/O pins.
All Virtex-II Pro IOBs (except RocketIO transceiver pins)
support IEEE 1149.1 and IEEE 1532 compatible Boundary-
Scan testing.
Figure 11: SSTL or HSTL SelectIO-Ultra Standards
8 mA
8 mA
8 mA
8 mA
8 mA
shows the SSTL2, SSTL18, and HSTL
OBUF
12 mA
12 mA
12 mA
12 mA
12 mA
V CCO
V REF
Clamp
Diode
16 mA
16 mA
16 mA
16 mA
16 mA
Functional Description
V CCAUX = 2.5V
V CCINT = 1.5V
DS031_24_100900
Module 2 of 4
PAD
24 mA
24 mA
24 mA
n/a
n/a
12