xq2vp40 Xilinx Corp., xq2vp40 Datasheet - Page 23

• Manufacturer Part Number: xq2vp40
• Description: Qpro Virtex-ii Pro 1.5v Platform Fpgas Complete Data Sheet
• Manufacturer: Xilinx Corp.

Input Path
The Virtex-II Pro IOB input path routes input signals directly
to internal logic and / or through an optional input flip-flop or
latch, or through the DDR input registers. An optional delay
element at the D-input of the storage element eliminates
pad-to-pad hold time. The delay is matched to the internal
clock-distribution delay of the Virtex-II Pro device, and when
used, assures that the pad-to-pad hold time is zero.
Each input buffer can be configured to conform to any of the
low-voltage signaling standards supported. In some of
these standards the input buffer utilizes a user-supplied
threshold voltage, V
constraints on which standards can be used in the same
bank. See I/O banking description.
Output Path
The output path includes a three-state output buffer that
drives the output signal onto the pad. The output and / or
the 3-state signal can be routed to the buffer directly from
the internal logic or through an output / three-state flip-flop
or latch, or through the DDR output / three-state registers.
Each output driver can be individually programmed for a
wide range of low-voltage signaling standards. In most
signaling standards, the output High voltage depends on an
externally supplied V
imposes constraints on which standards can be used in the
same bank. See I/O banking description.
I/O Banking
Some of the I/O standards described above require V
and V
and connected to device pins that serve groups of IOB
blocks, called banks. Consequently, restrictions exist about
which I/O standards can be combined within a given bank.
Eight I/O banks result from dividing each edge of the FPGA
into two banks, as shown in
bank has multiple V
connected to the same voltage. This voltage is determined
by the output standards in use.
Some input standards require a user-supplied threshold
voltage (V
configured as V
I/O pins in the bank assume this role.
V
only one V
However, for correct operation, all V
must be connected to the external reference voltage source.
DS136-2 (v2.0) December 20, 2007
Preliminary Product Specification
REF
pins within a bank are interconnected internally, thus
REF
voltages. These voltages are externally supplied
REF
REF
R
), and certain user-I/O pins are automatically
voltage can be used within each bank.
REF
CCO
REF
inputs. Approximately one in six of the
CCO
. The need to supply V
pins, all of which must be
voltage. The need to supply V
Figure 12
REF
and
pins in the bank
Figure
REF
13. Each
imposes
CCO
www.xilinx.com
CCO
X-Ref Target - Figure 12
X-Ref Target - Figure 13
The V
device pinout tables. Within a given package, the number of
V
device. In larger devices, more I/O pins convert to V
pins. Since these are always a superset of the V
used for smaller devices, it is possible to design a PCB that
permits migration to a larger device if necessary.
All V
connected to the V
smaller devices, some V
not connect within the package. These unconnected pins
can be left unconnected externally, or, if necessary, they can
be connected to V
REF
Figure 12: I/O Banks: Wire-Bond Packages (FG)
REF
Figure 13: I/O Banks: Flip-Chip Packages (FF)
and V
CCO
pins for the largest device anticipated must be
and the V
CCO
pins can vary depending on the size of
CCO
REF
REF
Bank 1
Bank 0
Bank 5
Bank 4
to permit migration to a larger device.
voltage and not used for I/O. In
CCO
Top View
Top View
pins for each bank appear in the
pins used in larger devices do
Bank 0
Bank 5
Bank 1
Bank 4
Functional Description
ug002_c2_014_041403
ds031_66_041403
Module 2 of 4
REF
REF
pins
13