xq2vp40 Xilinx Corp., xq2vp40 Datasheet - Page 7

• Manufacturer Part Number: xq2vp40
• Description: Qpro Virtex-ii Pro 1.5v Platform Fpgas Complete Data Sheet
• Manufacturer: Xilinx Corp.

clock output frequency equal to a fractional or integer multiple
of the input clock frequency. For exact timing parameters, see
"DC and Switching Characteristics" (Module
QPro Virtex-II Pro devices have 16 global clock MUX
buffers, with up to eight clock nets per quadrant. Each clock
MUX buffer can select one of the two clock inputs and
switch glitch-free from one clock to the other. Each DCM
can send up to four of its clock outputs to global clock
buffers on the same edge. Any global clock pin can drive
any DCM on the same edge.
Routing Resources
The IOB, CLB, block SelectRAM+, multiplier, and DCM
elements all use the same interconnect scheme and the
same access to the global routing matrix. Timing models
are shared, greatly improving the predictability of the
performance of high-speed designs.
There are a total of 16 global clock lines, with eight available
per quadrant. In addition, 24 vertical and horizontal long
lines per row or column, as well as massive secondary and
local routing resources, provide fast interconnect.
QPro Virtex-II Pro buffered interconnects are relatively
unaffected by net fanout, and the interconnect layout is
designed to minimize crosstalk.
Horizontal and vertical routing resources for each row or
column include:
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Boundary-Scan
Boundary-scan instructions and associated data registers
support a standard methodology for accessing and
configuring QPro Virtex-II Pro devices, complying with IEEE
IP Core and Reference Support
Intellectual Property is part of the Platform FPGA solution.
In addition to existing FPGA fabric cores, the next
subsections show some of the currently available hardware
and software intellectual properties specially developed for
QPro Virtex-II Pro devices by Xilinx. Each IP core is
modular, portable, Real-Time Operating System (RTOS)
independent, and CoreConnect compatible for ease of
design migration. Refer to
latest and most complete list of cores.
DS136-1 (v2.0) December 20, 2007
Preliminary Product Specification
24 long lines
120 hex lines
40 double lines
16 direct connect lines (total in all four directions)
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for the
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standards 1149.1 and 1532. A system mode and a test
mode are implemented. In system mode, a
QPro Virtex-II Pro device continues to function while
executing non-test boundary-scan instructions. In test mode,
boundary-scan test instructions control the I/O pins for
testing purposes. The QPro Virtex-II Pro Test Access Port
(TAP) supports BYPASS, PRELOAD, SAMPLE, IDCODE,
and USERCODE non-test instructions. The EXTEST,
INTEST, and HIGHZ test instructions are also supported.
Configuration
QPro Virtex-II Pro devices are configured by loading the
bitstream into internal configuration memory using one of
the following modes:
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A Data Encryption Standard (DES) decryptor is available
on-chip to secure the bitstreams. One or two triple-DES key
sets can be used to optionally encrypt the configuration data.
Readback and Integrated Logic Analyzer
Configuration data stored in QPro Virtex-II Pro
configuration memory can be read back for verification.
Along with the configuration data, the contents of all flip-
flops and latches, distributed SelectRAM+, and block
SelectRAM+ memory resources can be read back. This
capability is useful for real-time debugging.
The Xilinx ChipScope Integrated Logic Analyzer (ILA) cores
and Integrated Bus Analyzer (IBA) cores, along with the
ChipScope Pro Analyzer software, provide a complete
solution for accessing and verifying user designs within
QPro Virtex-II Pro devices.
Hardware Cores
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Software Cores
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Slave-serial mode
Master-serial mode
Slave SelectMAP mode
Master SelectMAP mode
Boundary-Scan mode (IEEE 1532)
Bus Infrastructure cores (arbiters, bridges, and more)
Memory cores (DDR, Flash, and more)
Peripheral cores (UART, IIC, and more)
Networking cores (ATM, Ethernet, and more)
Boot code
Test code
Device drivers
Protocol stacks
RTOS integration
Customized board support package
Introduction and Overview
Module 1 of 4
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