xq2vp40 Xilinx Corp., xq2vp40 Datasheet - Page 76

• Manufacturer Part Number: xq2vp40
• Description: Qpro Virtex-ii Pro 1.5v Platform Fpgas Complete Data Sheet
• Manufacturer: Xilinx Corp.

Configuration Timing
Configuration Memory Clearing Parameters
Power-up timing of configuration signals is shown in
X-Ref Target - Figure 2
Table 33: Power-Up Timing Characteristics
DS136-3 (v2.0) December 20, 2007
Preliminary Product Specification
Notes:
1.
Power-on reset
Program latency
CCLK (output) delay
Program pulse width
The M2, M1, and M0 mode pins should be set at a constant DC voltage level, either through pull-up or pull-down resistors, or tied directly to
ground or V
R
CCAUX
Description
. The mode pins should not be toggled during and after configuration.
M0, M1, M2*
PROG_B
(Required)
or Input)
INIT_B
(Output
CCLK
V
CC
Figure 2: Configuration Power-Up Timing
References
Figure
*Can be either 0 or 1, but must not toggle during and after configuration.
1
2
3
Figure
1
www.xilinx.com
T
POR
2; corresponding timing characteristics are listed in
2
T
PL
T
Symbol
PROGRAM
T
T
T
ICCK
POR
PL
T
ICCK
3
T
Value
DC and Switching Characteristics
PL
0.25
4.00
300
ds083-3_07_012004
4
+ 2
μs per frame, max
ms, max
μs, max
μs, min
ns, min
Units
Module 3 of 4
Table
33.
24