xq2vp40 Xilinx Corp., xq2vp40 Datasheet - Page 41

• Manufacturer Part Number: xq2vp40
• Description: Qpro Virtex-ii Pro 1.5v Platform Fpgas Complete Data Sheet
• Manufacturer: Xilinx Corp.

•
X-Ref Target - Figure 39
Control Pins and Attributes
Virtex-II Pro SelectRAM+ memory has two independent
ports with the control signals described in
control inputs including the clock have an optional inversion.
Table 17: Control Functions
Initial memory content is determined by the INIT_xx
attributes. Separate attributes determine the output register
value after device configuration (INIT) and SSR is asserted
(SRVAL). Both attributes (INIT_B and SRVAL) are available
for each port when a block SelectRAM+ resource is
configured as dual-port RAM.
DS136-2 (v2.0) December 20, 2007
Preliminary Product Specification
RAM Contents
Control Signal
NO_CHANGE
The NO_CHANGE option maintains the content of the
output registers, regardless of the write operation. The
clock edge during the write mode has no effect on the
content of the data output register DO. When the port is
configured as NO_CHANGE, only a read operation
loads a new value in the output register DO, as shown in
Figure
Data_out
Address
Data_in
Data_in
SSR
CLK
WE
CLK
EN
WE
39.
R
Figure 39: NO_CHANGE Mode
DI
New
Read and Write Clock
Enable affects Read, Write, Set, Reset
Write Enable
Set DO register to SRVAL (attribute)
Old
aa
Internal
Memory
Last Read Cycle Content (no change)
DO
Function
No change during write
Table
New
DS083-2_12_050901
17. All
www.xilinx.com
Total Amount of SelectRAM+ Memory
Virtex-II Pro SelectRAM+ memory blocks are organized in
multiple columns. The number of blocks per column
depends on the row size, the number of Processor Blocks,
and the number of RocketIO transceivers.
Table 18
amount of block SelectRAM+ memory available for each
Virtex-II Pro device. The 18 Kb SelectRAM+ blocks are
cascadable to implement deeper or wider single- or dual-port
memory resources.
Table 18: Virtex-II Pro SelectRAM+ Memory Available
Figure 40
XQ2VP4 device.
X-Ref Target - Figure 40
XQ2VP40
XQ2VP70
Device
Figure 40: XQ2VP4 Block RAM Column Layout
BRAM
Multiplier
Blocks
shows the number of columns as well as the total
shows the layout of the block RAM columns in the
Columns
DCM
DCM
10
14
CLBs
Serial Transceivers
Serial Transceivers
Blocks
RocketIO
RocketIO
192
328
Total SelectRAM+ Memory
CLBs
Functional Description
TM
TM
PPC405
in Kb
3,456
5,904
CLBs
CPU
DS083-2_11_010802
DCM
DCM
Module 2 of 4
3,538,944
6,045,696
in Bits
31