xq2vp40 Xilinx Corp., xq2vp40 Datasheet - Page 91

• Manufacturer Part Number: xq2vp40
• Description: Qpro Virtex-ii Pro 1.5v Platform Fpgas Complete Data Sheet
• Manufacturer: Xilinx Corp.

Table 4: QPro Virtex-II Pro Pin Definitions (Cont’d)
DS136-4 (v2.0) December 20, 2007
Preliminary Product Specification
Notes:
1.
2.
3.
Dedicated Pins:
Other Pins:
AVCCAUXRX#
AVCCAUXTX#
All dedicated pins (JTAG and configuration) are powered by V
For more information on BREFCLK, see
RocketIO™ Multi-Gigabit Transceivers (MGTs) are not supported in QPro Virtex-II Pro FPGAs.
BREFCLKP
VTRXPAD#
VTTXPAD#
PWRDWN_B
BREFCLKN,
HSWAP_EN
RXPPAD#
RXNPAD#
TXNPAD#
TXPPAD#
M2, M1, M0
Pin Name
DXN, DXP
GNDA#
PROG_B
V
V
DONE
RSVD
CCLK
V
V
GND
TDO
TMS
CCAUX
TCK
CCINT
TDI
BATT
CCO
R
(3)
(3)
(3)
(3)
(3)
(2,3)
(3)
(3)
(1)
(3)
(3)
(unsupported)
Input/Output
Input/Output
(open-drain)
Direction
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
N/A
N/A
"BREFCLK Pin Definitions," page
Configuration clock. Output in Master mode or Input in Slave mode.
Active Low asynchronous reset to configuration logic. This pin has a permanent weak pull-
up resistor.
DONE is a bidirectional signal with an optional internal pull-up resistor. As an output, this pin
indicates completion of the configuration process. As an input, a Low level on DONE can be
configured to delay the start-up sequence.
Configuration mode selection. Pin is biased by V
not connect to 3.3V unless 100Ω series resistors are used. The mode pins are not to be
toggled (changed) while in operation during and after configuration.
Enable I/O pull-ups during configuration.
Boundary-Scan Clock. This pin is 3.3V compatible.
Boundary-Scan Data Input. This pin is 3.3V compatible.
Boundary-Scan Data Output. Pin is open-drain and can be pulled up to 3.3V. It is
recommended that the external pull-up be greater than 200Ω. There is no internal pull-up.
Boundary-Scan Mode Select. This pin is 3.3V compatible.
Active Low power-down pin (unsupported). Driving this pin Low can adversely affect device
operation and configuration. PWRDWN_B is internally pulled High, which is its default state.
It does not require an external pull-up.
Temperature-sensing diode pins (Anode: DXP, Cathode: DXN).
Decryptor key memory backup supply. (Connect to V
Reserved pin - do not connect.
Power-supply pins for the output drivers (per bank).
Power-supply pins for auxiliary circuits.
Power-supply pins for the internal core logic.
Ground.
Analog power supply for receive circuitry of the RocketIO MGT (2.5V).
Analog power supply for transmit circuitry of the RocketIO MGT (2.5V).
Differential clock input that clocks the RocketIO X MGTs populating the same side of the chip
(top or bottom). Can also drive DCMs for RocketIO X MGT use.
Receive termination supply for the RocketIO MGT (1.8V - 2.8V).
Transmit termination supply for the RocketIO MGT (1.8V - 2.8V).
Ground for the analog circuitry of the RocketIO MGT.
Positive differential receive port of the RocketIO MGT.
Negative differential receive port of the RocketIO MGT.
Positive differential transmit port of the RocketIO MGT.
Negative differential transmit port of the RocketIO MGT.
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CCAUX
(independent of the bank V
4.
Description
CCAUX
CCO
CCAUX
(must be 2.5V). These pins should
voltage).
or GND if battery not used.)
Pinout Information
Module 4 of 4
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