xq2vp40 Xilinx Corp., xq2vp40 Datasheet - Page 39

• Manufacturer Part Number: xq2vp40
• Description: Qpro Virtex-ii Pro 1.5v Platform Fpgas Complete Data Sheet
• Manufacturer: Xilinx Corp.

18 Kb Block SelectRAM+ Resources
Introduction
Virtex-II Pro devices incorporate large amounts of 18 Kb
block SelectRAM+ resources. These complement the
distributed SelectRAM+ resources that provide shallow
RAM structures implemented in CLBs. Each Virtex-II Pro
block SelectRAM+ resource is an 18 Kb true dual-port RAM
with two independently clocked and independently
controlled synchronous ports that access a common
storage area. Both ports are functionally identical. CLK, EN,
WE, and SSR polarities are defined through configuration.
Each port has the following types of inputs: Clock and Clock
Enable, Write Enable, Set/Reset, and Address, as well as
separate Data/parity data inputs (for write) and Data/parity
data outputs (for read).
Operation is synchronous; the block SelectRAM+ behaves
like a register. Control, address and data inputs must (and
need only) be valid during the set-up time window prior to a
rising (or falling, a configuration option) clock edge. Data
outputs change as a result of the same clock edge.
Configuration
Virtex-II Pro block SelectRAM+ supports various
configurations, including single- and dual-port RAM and
various data/address aspect ratios. Supported memory
configurations for single- and dual-port modes are shown in
Table
Table 14: Dual- and Single-Port Configurations
Table 15: Dual-Port Mode Configurations
DS136-2 (v2.0) December 20, 2007
Preliminary Product Specification
Port A
Port B
Port A
Port B
Port A
Port B
Port A
Port B
Port A
Port B
Port A
Port B
14.
16K x 1 bit
8K x 2 bits
4K x 4 bits
R
512 x 36
512 x 36
16K x 1
16K x 1
1K x 18
1K x 18
8K x 2
8K x 2
4K x 4
4K x 4
2K x 9
2K x 9
512 x 36
512 x 36 bits
16K x 1
1K x 18
1K x 18
1K x 18 bits
8K x 2
8K x 2
4K x 4
4K x 4
2K x 9
2K x 9
2K x 9 bits
www.xilinx.com
512 x 36
16K x 1
1K x 18
4K x 4
8K x 2
2K x 9
4K x 4
2K x 9
Single-Port Configuration
As a single-port RAM, the block SelectRAM+ has access to
the 18 Kb memory locations in any of the 2K x 9-bit,
1K x 18-bit, or 512 x 36-bit configurations and to 16 Kb
memory locations in any of the 16K x 1-bit, 8K x 2-bit, or
4K x 4-bit configurations. The advantage of the 9-bit, 18-bit
and 36-bit widths is the ability to store a parity bit for each
eight bits. Parity bits must be generated or checked
externally in user logic. In such cases, the width is viewed
as 8 + 1, 16 + 2, or 32 + 4. These extra parity bits are stored
and behave exactly as the other bits, including the timing
parameters. Video applications can use the 9-bit ratio of
Virtex-II Pro block SelectRAM+ memory to advantage.
Each block SelectRAM+ cell is a fully synchronous memory
as illustrated in
bus widths are identical.
X-Ref Target - Figure 35
Dual-Port Configuration
As a dual-port RAM, each port of block SelectRAM+ has
access to a common 18 Kb memory resource. These are
fully synchronous ports with independent control signals for
each port. The data widths of the two ports can be configured
independently, providing built-in bus-width conversion.
Table 15
ports A and B.
Figure 35: 18 Kb Block SelectRAM+ Memory in Single-
illustrates the different configurations available on
512 x 36
16K x 1
1K x 18
2K x 9
8K x 2
4K x 4
Figure
DIP
ADDR
WE
EN
SSR
DI
CLK
18-Kbit Block SelectRAM
35. Input data bus and output data
Port Mode
512 x 36
16K x 1
1K x 18
8K x 2
Functional Description
DOP
DO
DS031_10_102000
512 x 36
16K x 1
Module 2 of 4
29