xq2vp40 Xilinx Corp., xq2vp40 Datasheet - Page 21

• Manufacturer Part Number: xq2vp40
• Description: Qpro Virtex-ii Pro 1.5v Platform Fpgas Complete Data Sheet
• Manufacturer: Xilinx Corp.

Each register or latch, independent of all other registers or
latches, can be configured as follows:
•
•
•
•
X-Ref Target - Figure 8
X-Ref Target - Figure 9
DS136-2 (v2.0) December 20, 2007
Preliminary Product Specification
No set or reset
Synchronous set
Synchronous reset
Synchronous set and reset
R
registers
Shared
by all
(O/T) CLK1
(O/T) CLK2
DCM
0°
(O/T) CE
(O/T) 1
(O/T) 2
REV
SR
D1
D2
CLK1
CLK2
Figure 9: Register / Latch Configuration in an IOB Block
Q1
Q2
Figure 8: Double Data Rate Registers
DDR MUX
FDDR
D1
CE
CK1
D2
CE
CK2
SR REV
SR REV
FF
LATCH
FF
LATCH
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Q
Q1
Q2
Attribute INIT1
Attribute INIT1
•
•
•
The synchronous reset overrides a set, and an asynchronous
clear overrides a preset (refer to
180° 0°
DCM
DDR MUX
Asynchronous set (preset)
Asynchronous reset (clear)
Asynchronous set and reset (preset and clear)
FF1
FF2
INIT0
SRHIGH
SRLOW
INIT0
SRHIGH
SRLOW
D1
D2
CLK1
CLK2
Q1
Q2
Reset Type
DDR MUX
SYNC
ASYNC
Figure
FDDR
Functional Description
DS083-2_26_121207
DS031_25_110300
(OQ or TQ)
9).
Q
Module 2 of 4
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