xq2vp40 Xilinx Corp., xq2vp40 Datasheet - Page 90

• Manufacturer Part Number: xq2vp40
• Description: Qpro Virtex-ii Pro 1.5v Platform Fpgas Complete Data Sheet
• Manufacturer: Xilinx Corp.

QPro Virtex-II Pro Pin Definitions
This section describes the pinouts for QPro Virtex-II Pro devices in the following packages:
•
•
•
All of the devices supported in a particular package are pinout-compatible and are listed in the same table (one table per
package). Pins that are not available for smaller devices are listed in right-hand columns as No Connects.
Each device is split into eight I/O banks to allow for flexibility in the choice of I/O standards. Global pins, including JTAG,
configuration, and power/ground pins, are listed at the end of each table.
All QPro Virtex-II Pro pinout tables are available online (at
Pin Definitions
Table 4
Table 4: QPro Virtex-II Pro Pin Definitions
DS136-4 (v2.0) December 20, 2007
Preliminary Product Specification
User I/O Pins:
Dual-Function Pins:
"ZZZ" (Dual Function) Definitions:
D0/DIN, D1, D2, D3, D4,
FG676 Fine-Pitch BGA Package
EF1152, and FF1152 Flip-Chip Fine-Pitch BGA Packages
EF1704, and FF1704 Flip-Chip Fine-Pitch BGA Packages
IO_LXXY_#/ZZZ
BUSY/DOUT
GCLKx (S/P)
IO_LXXY_#
D5, D6, D7
Pin Name
RDWR_B
provides a description of each pin type listed in QPro Virtex-II Pro pinout tables.
INIT_B
CS_B
V
VRP
VRN
REF
R
The dual-function pins are labelled “IO_LXXY_#/ ZZZ”, where "ZZZ" can be one of the following pins:
• Per Bank - VRP, VRN, or VREF
• Globally - GCLKX(S/P), BUSY/DOUT, INIT_B, D0/DIN – D7, RDWR_B, or CS_B
These dual functions are defined in the following section:
Input/Output/Bi
Input/Output
Input/Output
Bidirectional
(open-drain)
directional
Direction
Output
Input
Input
Input
Input
Input
All user I/O pins are capable of differential signalling and can implement LVDS, ULVDS,
BLVDS, LVPECL, or LDT pairs. Each user I/O is labeled “IO_LXXY_#”, where:
• IO indicates a user I/O pin.
• LXXY indicates a differential pair, with XX a unique pair in the bank and Y = P/N for the
• # indicates the bank number (0 through 7)
• In SelectMAP mode, D0 through D7 are configuration data pins. These pins become user
• In bit-serial modes, DIN (D0) is the single-data input. This pin becomes a user I/O after
In SelectMAP mode, this is the active-low Chip Select signal. The pin becomes a user I/O
after configuration, unless the SelectMAP port is retained.
In SelectMAP mode, this is the active-low Write Enable signal. The pin becomes a user I/O
after configuration, unless the SelectMAP port is retained.
• In SelectMAP mode, BUSY controls the rate at which configuration data is loaded. The
• In bit-serial modes, DOUT provides preamble and configuration data to downstream
When Low, this pin indicates that the configuration memory is being cleared. When held Low,
the start of configuration is delayed. During configuration, a Low on this output indicates that
a configuration data error has occurred. The pin becomes a user I/O after configuration.
These are clock input pins that connect to Global Clock Buffers. These pins become regular
user I/Os when not needed for clocks. In addition, These pins can be used to clock the
RocketIO transceiver. See the
guidelines and BREFCLK-specific pins, by device.
This pin is for the DCI voltage reference resistor of P transistor (per bank).
This pin is for the DCI voltage reference resistor of N transistor (per bank).
These are input threshold voltage pins. They become user I/Os when an external threshold
voltage is not needed (per bank).
positive and negative sides of the differential pair.
I/Os after configuration, unless the SelectMAP port is retained.
configuration.
pin becomes a user I/O after configuration, unless the SelectMAP port is retained.
devices in a daisy-chain. The pin becomes a user I/O after configuration.
www.xilinx.com
www.xilinx.com
UG024
).
Table 4
, RocketIO
Description
provides definitions for all pin types.
™
Transceiver User Guide,
Pinout Information
Module 4 of 4
for design
2