xq2vp40 Xilinx Corp., xq2vp40 Datasheet - Page 83

• Manufacturer Part Number: xq2vp40
• Description: Qpro Virtex-ii Pro 1.5v Platform Fpgas Complete Data Sheet
• Manufacturer: Xilinx Corp.

Input Clock Tolerances
Table 42: Input Clock Tolerances
DS136-3 (v2.0) December 20, 2007
Preliminary Product Specification
Notes:
1.
2.
3.
Input Clock Low/High Pulse Width
Input Clock Cycle-Cycle Jitter (Low Frequency Mode)
Input Clock Cycle-Cycle Jitter (High Frequency Mode)
Input Clock Period Jitter (Low Frequency Mode)
Input Clock Period Jitter (High Frequency Mode)
Feedback Clock Path Delay Variation
PSCLK
PSCLK and CLKIN
CLKIN (using DLL outputs)
CLKIN (using CLKFX outputs)
CLKIN (using DLL outputs)
CLKIN (using CLKFX outputs)
CLKIN (using DLL outputs)
CLKIN (using CLKFX outputs)
CLKIN (using DLL outputs)
CLKIN (using CLKFX outputs)
CLKFB off-chip feedback
“DLL outputs” is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
If both DLL and CLKFX outputs are used, follow the more restrictive specification.
If DCM phase shift feature is used and CLKIN frequency > 200 Mhz, CLKIN duty cycle must be within ±5% (45/55 to 55/45).
Description
R
(3)
(1)
(1)
(1)
(1)
(2)
(2)
(2)
(2)
PSCLK_PULSE
PSCLK_PULSE and
CLKIN_PULSE
CLKIN_CYC_JITT_DLL_LF
CLKIN_CYC_JITT_FX_LF
CLKIN_CYC_JITT_DLL_HF
CLKIN_CYC_JITT_FX_HF
CLKIN_PER_JITT_DLL_LF
CLKIN_PER_JITT_FX_LF
CLKIN_PER_JITT_DLL_HF
CLKIN_PER_JITT_FX_HF
CLKFB_DELAY_VAR_EXT
Symbol
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< 1MHz
1 – 10 MHz
10 – 25 MHz
25 – 50 MHz
50 – 100 MHz
100 – 150 MHz
150 – 200 MHz
200 – 250 MHz
250 – 300 MHz
300 – 350 MHz
350 – 400 MHz
> 400 MHz
Constraints
F
CLKIN
25.00
25.00
10.00
5.00
3.00
2.40
2.00
1.80
1.50
1.30
1.15
1.05
Min
-6
DC and Switching Characteristics
±300
±300
±150
±150
Max
Speed Grade
±1
±1
±1
±1
±1
25.00
25.00
10.00
5.00
3.00
2.40
2.00
1.80
1.50
1.30
1.15
1.05
Min
-5
±300
±300
±150
±150
Max
±1
±1
±1
±1
±1
Module 3 of 4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
ns
ns
ns
ns
ns
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