xq2vp40 Xilinx Corp., xq2vp40 Datasheet - Page 44

• Manufacturer Part Number: xq2vp40
• Description: Qpro Virtex-ii Pro 1.5v Platform Fpgas Complete Data Sheet
• Manufacturer: Xilinx Corp.

Global clocks are driven by dedicated clock buffers (BUFG),
which can also be used to gate the clock (BUFGCE) or to
multiplex between two independent clock inputs (BUFGMUX).
The most common configuration option of this element is as
a buffer. A BUFG function in this (global buffer) mode, is
shown in
X-Ref Target - Figure 46
The Virtex-II Pro global clock buffer BUFG can also be
configured as a clock enable/disable circuit
well as a two-input clock multiplexer
description of these two options is provided below. Each of
them can be used in either of two modes, selected by
configuration: rising clock edge or falling clock edge.
X-Ref Target - Figure 47
X-Ref Target - Figure 48
This section describes the rising clock edge option. For the
opposite option, falling clock edge, just change all "rising"
references to "falling" and all "High" references to "Low",
except for the description of the CE and S levels. The rising
clock edge option uses the BUFGCE and BUFGMUX
primitives. The falling clock edge option uses the
BUFGCE_1 and BUFGMUX_1 primitives.
BUFGCE
If the CE input is active (High) prior to the incoming rising
clock edge, this Low-to-High-to-Low clock pulse passes
through the clock buffer. Any level change of CE during the
incoming clock High time has no effect.
If the CE input is inactive (Low) prior to the incoming rising
clock edge, the following clock pulse does not pass through
DS136-2 (v2.0) December 20, 2007
Preliminary Product Specification
Figure 48: Virtex-II Pro BUFGMUX Function
Figure 47: Virtex-II Pro BUFGCE Function
Figure 46: Virtex-II Pro BUFG Function
Figure
R
46.
S
CE
I
I
I
I
0
1
BUFGMUX
BUFGCE
BUFG
DS083-2_63_121701
DS031_61_101200
DS031_62_101200
O
(Figure
O
O
48). A functional
(Figure
47), as
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the clock buffer, and the output stays Low. Any level change
of CE during the incoming clock High time has no effect. CE
must not change during a short setup window just prior to
the rising clock edge on the BUFGCE input I. Violating this
setup time requirement can result in an undefined runt
pulse output.
BUFGMUX
BUFGMUX can switch between two unrelated, even
asynchronous clocks. Basically, a Low on S selects the I
input, a High on S selects the I
clock to the other is done in such a way that the output High
and Low time is never shorter than the shortest High or Low
time of either input clock. As long as the presently selected
clock is High, any level change of S has no effect.
If the presently selected clock is Low while S changes, or if
it goes Low after S has changed, the output is kept Low until
the other ("to-be-selected") clock has made a transition
from High to Low. At that instant, the new clock starts
driving the output.
The two clock inputs can be asynchronous with regard to
each other, and the S input can change at any time, except
for a short setup time prior to the rising edge of the presently
selected clock (I0 or I1). Violating this setup time
requirement can result in an undefined runt pulse output.
All Virtex-II Pro devices have 16 global clock multiplexer
buffers.
Figure 49
•
•
•
•
•
•
X-Ref Target - Figure 49
Out
I 0
I1
S
The current clock is CLK0.
S is activated High.
If CLK0 is currently High, the multiplexer waits for CLK0
to go Low.
Once CLK0 is Low, the multiplexer output stays Low
until CLK1 transitions High to Low.
When CLK1 transitions from High to Low, the output
switches to CLK1.
No glitches or short pulses can appear on the output.
Figure 49: Clock Multiplexer Waveform Diagram
shows a switchover from I0 to I1:
Wait for Low
Switch
1
input. Switching from one
Functional Description
DS083-2_46_020604
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