xq2vp40 Xilinx Corp., xq2vp40 Datasheet - Page 87

• Manufacturer Part Number: xq2vp40
• Description: Qpro Virtex-ii Pro 1.5v Platform Fpgas Complete Data Sheet
• Manufacturer: Xilinx Corp.

Table 51: Example Pin-to-Pin Setup/Hold: Source-Synchronous Configuration
Source Synchronous Timing Budgets
This section describes how to use the parameters provided
in
page 34
following analysis provides information necessary for
determining QPro Virtex-II Pro contributions to an overall
system timing analysis; no assumptions are made about the
effects of Inter-Symbol Interference or PCB skew.
QPro Virtex-II Pro Transmitter Data-Valid Window (T
T
synchronous data bus at the pins of the device and is
calculated as follows:
Notes:
1.
2.
3.
DS136-3 (v2.0) December 20, 2007
Preliminary Product Specification
Notes:
1.
2.
Example Data Input Set-Up and Hold Times
Relative to a Forwarded Clock Input Pin,
Using DCM and Global Clock Buffer.
Values represent an 18-bit bus located in
Banks 2, 3, 6, or 7 and grouped to one
Horizontal Global Clock Line. TRACE must be
used to determine the actual values for any
given design.
For situations where clock and data inputs
conform to different standards, adjust the setup
and hold values accordingly using the values
shown in
Standard Adjustments," page
No Delay
Global Clock and IFF
X
"Source-Synchronous Switching Characteristics,"
♦
♦
is the minimum aggregate valid data period for a source-
T
TCKSKEW
Jitter values and accumulation methodology to be provided in a
future release of this document. The absolute period jitter values
found in the
particular DCM output clock used to clock the IOB FF can be
used for a best case analysis.
This value depends on the clocking methodology used. See
Note1 for
This value represents the worst-case clock-tree skew observable
between sequential I/O elements. Significantly less clock-tree
skew exists for I/O registers that are close to each other and fed
by the same or adjacent clock-tree branches. Use the Xilinx
FPGA_Editor and Timing Analyzer tools to evaluate clock skew
specific to your application.
The timing values were measured using the fine-phase adjustment feature of the DCM. These measurements include:
Package skew is not included in these measurements.
IFF = Input Flip-Flop
X
CLK0 and CLK180 DCM jitter
Worst-case duty-cycle distortion using CLK0 and CLK180, T
= Data Period - [Jitter
to develop system-specific timing budgets. The
"IOB Input Switching Characteristics
R
Table 48, page
"DCM Timing Parameters," page 30
(3)
Description
+ TPKGSKEW
(2)
with DCM
34.
10.
(1)
+ Duty Cycle Distortion
(4)
]
(1)
section of the
T
PSDCM_0
www.xilinx.com
Symbol
(2)
DCD_CLK180
X
+
/T
)
PHDCM_0
4.
QPro Virtex-II Pro Receiver Data-Valid Window (R
R
a source-synchronous data bus at the pins of the device
and is calculated as follows:
Notes:
1.
2.
3.
X
♦
♦
♦
♦
is the required minimum aggregate valid data period for
These values represent the worst-case skew between any two
balls of the package: shortest flight time to longest flight time from
pad to ball.
R
This parameter indicates the total sampling error of
QPro Virtex-II Pro DDR input registers across voltage,
temperature, and process. The characterization methodology
uses the DCM to capture the DDR input registers’ edges of
operation. These measurements include:
These measurements do not include package or clock tree skew.
This value represents the worst-case clock-tree skew observable
between sequential I/O elements. Significantly less clock-tree
skew exists for I/O registers that are close to each other and fed
by the same or adjacent clock-tree branches. Use the Xilinx
FPGA_Editor and Timing Analyzer tools to evaluate clock skew
specific to your application.
These values represent the worst-case skew between any two
balls of the package: shortest flight time to longest flight time from
pad to ball.
CLK0 and CLK180 DCM jitter in a quiet system
Worst-case duty-cycle distortion
DCM accuracy (phase offset)
DCM phase shift resolution.
X
= [TSAMP
XQ2VP40
XQ2VP70
Device
(1)
+ TCKSKEW
DC and Switching Characteristics
0.18/ 0.38
-6
Speed Grade
(2)
+ TPKGSKEW
0.27/ 0.29
0.18/ 0.38
-5
Module 3 of 4
(3)
Units
ns
ns
]
X
)
35