xq2vp40 Xilinx Corp., xq2vp40 Datasheet - Page 20

• Manufacturer Part Number: xq2vp40
• Description: Qpro Virtex-ii Pro 1.5v Platform Fpgas Complete Data Sheet
• Manufacturer: Xilinx Corp.

Table 3: Supported DCI I/O Standards
Logic Resources
IOB blocks include six storage elements, as shown in
Each storage element can be configured either as an edge-
triggered D-type flip-flop or as a level-sensitive latch. On the
input, output, and three-state path, one or two DDR
registers can be used.
Double data rate is directly accomplished by the two
registers on each path, clocked by the rising edges (or
falling edges) from two different clock nets. The two clock
signals are generated by the DCM and must be 180
degrees out of phase, as shown in
are two input, output, and three-state data signals, each
being alternately clocked out.
This DDR mechanism can be used to mirror a copy of the
clock on the output. This is useful for propagating a clock
along the data that has an identical delay. It is also useful for
multiple clock generation, where there is a unique clock
DS136-2 (v2.0) December 20, 2007
Preliminary Product Specification
Notes:
1.
2.
3.
4.
LVDCI_33
LVDCI_25
LVDCI_DV2_25
LVDCI_18
LVDCI_DV2_18
LVDCI_15
LVDCI_DV2_15
GTL_DCI
GTLP_DCI
HSTL_I_DCI
HSTL_II_DCI
HSTL_III_DCI
HSTL_IV_DCI
HSTL_I_DCI_18
HSTL_II_DCI_18
HSTL_III_DCI_18
HSTL_IV_DCI_18
SSTL2_I_DCI
SSTL2_II_DCI
SSTL18_I_DCI
SSTL18_II_DCI
LVDS_25_DCI
LVDSEXT_25_DCI
I/O Standard
LVDCI_XX is LVCMOS output controlled impedance buffers,
matching all or half of the reference resistors.
These are SSTL compatible.
SSTL18_I is not a JEDEC-supported standard.
Locations marked with a dash indicate no requirement.
(1)
R
(2)
(2)
(3)
Output
V
3.3
2.5
2.5
1.8
1.8
1.5
1.5
1.2
1.5
1.5
1.5
1.5
1.5
1.8
1.8
1.8
1.8
2.5
2.5
1.8
1.8
2.5
2.5
CCO
Input
V
1.8
3.3
2.5
2.5
1.8
1.8
1.5
1.5
1.2
1.5
1.5
1.5
1.5
1.5
1.8
1.8
1.8
2.5
2.5
1.8
1.8
2.5
2.5
CCO
Figure 8, page
Input
V
0.75
0.75
1.25
1.25
–
0.8
1.0
0.9
0.9
0.9
0.9
1.1
1.1
0.9
0.9
REF
–
–
–
–
–
–
–
–
(4)
Termination
11. There
Series
Series
Series
Series
Series
Series
Series
Single
Single
Single
Single
Single
Single
Type
Split
Split
Split
Split
Split
Split
Split
Split
Split
Split
Figure
www.xilinx.com
7.
driver for every clock load. Virtex-II Pro devices can
produce many copies of a clock with very little skew.
Each group of two registers has a clock enable signal (ICE
for the input registers, OCE for the output registers, and
TCE for the three-state registers). The clock enable signals
are active High by default. If left unconnected, the clock
enable for that storage element defaults to the active state.
X-Ref Target - Figure 7
Each IOB block has common synchronous or asynchronous
set and reset (SR and REV signals). Two neighboring IOBs
have a shared routing resource connecting the ICLK and
OTCLK pins on pairs of IOBs. If two adjacent IOBs using
DDR registers do not share the same clock signals on their
clock pins (ICLK1, ICLK2, OTCLK1, and OTCLK2), one of
the clock signals will be unroutable.
The IOB pairing is identical to the LVDS IOB pairs. Hence,
the package pin-out table can also be used for pin
assignment to avoid conflict.
SR forces the storage element into the state specified by
the SRHIGH or SRLOW attribute. SRHIGH forces a logic 1.
SRLOW forces a logic “0”. When SR is used, a second input
(REV) forces the storage element into the opposite state.
The reset condition predominates over the set condition.
The initial state after configuration or global initialization
state is defined by a separate INIT0 and INIT1 attribute. By
default, the SRLOW attribute forces INIT0, and the SRHIGH
attribute forces INIT1.
For each storage element, the SRHIGH, SRLOW, INIT0,
and INIT1 attributes are independent. Synchronous or
asynchronous set / reset is consistent in an IOB block.
All the control signals have independent polarity. Any
inverter placed on a control input is automatically absorbed.
OCK2
OCK2
OCK1
OCK1
Reg
Reg
Reg
Reg
Figure 7: Virtex-II Pro IOB Block
DDR mux
DDR mux
3-State
Output
IOB
Functional Description
ICK1
ICK2
Reg
Reg
Input
PAD
DS031_29_100900
Module 2 of 4
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