AT83C51SND1C_03 ATMEL [ATMEL Corporation], AT83C51SND1C_03 Datasheet - Page 103

• Manufacturer Part Number: AT83C51SND1C_03
• Description: Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface
• Manufacturer: ATMEL [ATMEL Corporation]

4109E–8051–06/03
Table 96. UEPSTAX Register
UEPSTAX (S:CEh) – USB Endpoint X Status and Control Register (X = EPNUM set in UEPNUM
Number
DIR
Bit
7
7
6
Mnemonic Description
RXOUTB1
RXOUTB1
DIR
Bit
6
Control Endpoint Direction Bit
This bit is relevant only if the endpoint is configured in Control type.
Set for the data stage. Clear otherwise.
Note: This bit should be configured on RXSETUP interrupt before any other bit is
changed. This also determines the status phase (IN for a control write and OUT
for a control read). This bit should be cleared for status stage of a Control Out
transaction.
Received OUT Data Bank 1 for Endpoints 1 and 2 (Ping-pong mode)
This bit is set by hardware after a new packet has been stored in the endpoint
FIFO data bank 1 (only in Ping-pong mode). Then, the endpoint interrupt is
triggered if enabled and all the following OUT packets to the endpoint bank 1 are
rejected (NAK’ed) until this bit has been cleared, excepted for Isochronous
Endpoints.
This bit should be cleared by the device firmware after reading the OUT data
from the endpoint FIFO.
STALLRQ
5
TXRDY
4
STLCRC
3
RXSETUP
AT8xC51SND1C
2
RXOUTB0
1
TXCMP
0
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