AT83C51SND1C_03 ATMEL [ATMEL Corporation], AT83C51SND1C_03 Datasheet - Page 148

• Manufacturer Part Number: AT83C51SND1C_03
• Description: Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface
• Manufacturer: ATMEL [ATMEL Corporation]

Slave Mode
Figure 114. SPI Slave Mode Block Diagram
Note:
Bit Rate
148
1. MSTR bit in SPCON is cleared to select slave mode.
AT8xC51SND1C
MISO/P4.2
MOSI/P4.1
SCK/P4.2
SS/P4.3
The SPI operates in slave mode when the MSTR bit in SPCON is cleared and data has
been loaded in SPDAT.
Figure 114 shows the SPI block diagram in slave mode. In slave mode, before a data
transmission occurs, the SS pin of the slave SPI must be asserted to low level. SS must
remain low until the transmission of the Byte is complete. In the slave SPI module, data
enters the shift register through the MOSI pin under the control of the serial clock pro-
vided by the master SPI module on the SCK input pin. When the master starts a
transmission, the data in the shift register begins shifting out on the MISO pin. The end
of transfer is signaled by SPIF being set.
When the AT8xC51SND1C is the only slave on the bus, it can be useful not to use SS#
pin and get it back to I/O functionality. This is achieved by setting SSDIS bit in SPCON.
This bit has no effect when CPHA is cleared (see Section "SS Management",
page 150).
The bit rate can be selected from seven predefined bit rates using the SPR2, SPR1 and
SPR0 control bits in SPCON according to Table 131. These bit rates are derived from
the peripheral clock (F
"Oscillator", page 12.
SPCON.5
SSDIS
Control and Clock Logic
SPCON.2
CPHA
PER
) issued from the Clock Controller block as detailed in Section
SPCON.3
CPOL
I
SPSTA.7
SPIF
8-bit Shift Register
SPDAT RD
SPDAT WR
Q
4109E–8051–06/03