AT83C51SND1C_03 ATMEL [ATMEL Corporation], AT83C51SND1C_03 Datasheet - Page 46

• Manufacturer Part Number: AT83C51SND1C_03
• Description: Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface
• Manufacturer: ATMEL [ATMEL Corporation]

Power Management
Reset
Cold Reset
46
AT8xC51SND1C
2 power reduction modes are implemented in the AT8xC51SND1C: the Idle mode and
the Power-down mode. These modes are detailed in the following sections. In addition
to these power reduction modes, the clocks of the core and peripherals can be dynami-
cally divided by 2 using the X2 mode detailed in section “X2 Feature”, page 12.
In order to start-up (cold reset) or to restart (warm reset) properly the microcontroller, an
high level has to be applied on the RST pin. A bad level leads to a wrong initialization of
the internal registers like SFRs, Program Counter… and to unpredictable behavior of
the microcontroller. A proper device reset initializes the AT8xC51SND1C and vectors
the CPU to address 0000h. RST input has a pull-down resistor allowing power-on reset
by simply connecting an external capacitor to V
can be applied either directly on the RST pin or indirectly by an internal reset source
such as the watchdog timer. Resistor value and input characteristics are discussed in
the Section “DC Characteristics” of the AT8xC51SND1C datasheet. The status of the
Port pins during reset is detailed in Table 57.
Figure 24. Reset Circuitry and Power-On Reset
Table 57. Pin Conditions in Special Operating Modes
Note:
2 conditions are required before enabling a CPU start-up:
•
•
If one of these 2 conditions are not met, the microcontroller does not start correctly and
can execute an instruction fetch from anywhere in the program space. An active level
applied on the RST pin must be maintained till both of the above conditions are met. A
reset is active when the level V
period of time where V
taken into account to determine the reset pulse width:
•
•
To determine the capacitor value to implement, the highest value of these 2 parameters
has to be chosen. Table 58 gives some capacitor values examples for a minimum R
of 50 KΩ and different oscillator startup and V
Reset
Idle
Power-down
V
The level on X1 input pin must be outside the specification (V
V
Oscillator startup time.
RST
Mode
DD
DD
1. Refer to section “Audio Output Interface”, page 73.
must reach the specified V
rise time,
RST input circuitry
VDD
VSS
Floating
Port 0
P
Data
Data
DD
and the oscillator are not stabilized. 2 parameters have to be
Port 1
High
Data
Data
IH1
DD
Port 2
High
Data
Data
is reached and when the pulse width covers the
range
Port 3
High
Data
Data
DD
From Internal
Reset Source
To CPU Core
and Peripherals
DD
rise times.
as shown in Figure 24. A warm reset
Port 4
High
Data
Data
Port 5
High
Data
Data
IH
Power-on Reset
, V
VDD
IL
)
+
Floating
MMC
Data
Data
4109E–8051–06/03
RST
Audio
Data
Data
1
RST