AT83C51SND1C_03 ATMEL [ATMEL Corporation], AT83C51SND1C_03 Datasheet - Page 160

• Manufacturer Part Number: AT83C51SND1C_03
• Description: Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface
• Manufacturer: ATMEL [ATMEL Corporation]

Bit Rate
Master Transmitter Mode
160
AT8xC51SND1C
The bit rate can be selected from seven predefined bit rates or from a programmable bit
rate generator using the SSCR2, SSCR1, and SSCR0 control bits in SSCON (see
Table 142). The predefined bit rates are derived from the peripheral clock (F
from the Clock Controller block as detailed in section "Oscillator", page 12, while bit rate
generator is based on timer 1 overflow output.
Table 135. Serial Clock Rates
Note:
In the master transmitter mode, a number of data Bytes are transmitted to a slave
receiver (see Figure 125). Before the master transmitter mode can be entered, SSCON
must be initialized as follows:
SSCR2:0 define the serial bit rate (see Table 135). SSPE must be set to enable the con-
troller. SSSTA, SSSTO and SSI must be cleared.
The master transmitter mode may now be entered by setting the SSSTA bit. The TWI
logic will now monitor the TWI bus and generate a START condition as soon as the bus
becomes free. When a START condition is transmitted, the serial interrupt flag (SSI bit
in SSCON) is set, and the status code in SSSTA is 08h. This status must be used to
vector to an interrupt routine that loads SSDAT with the slave address and the data
direction bit (SLA+W). The serial interrupt flag (SSI) must then be cleared before the
serial transfer can continue.
When the slave address and the direction bit have been transmitted and an acknowl-
edgment bit has been received, SSI is set again and a number of status code in SSSTA
are possible. There are 18h, 20h or 38h for the master mode and also 68h, 78h or B0h if
the slave mode was enabled (SSAA = logic 1). The appropriate action to be taken for
each of these status code is detailed in Table 136. This scheme is repeated until a
STOP condition is transmitted.
SSPE and SSCR2:0 are not affected by the serial transfer and are not referred to in
Table 136. After a repeated START condition (state 10h) the controller may switch to
the master receiver mode by loading SSDAT with SLA+R.
2
0
0
0
0
1
1
1
1
Bit Rate
SSCR2
SSCRx
1
0
0
1
1
0
0
1
1
1. These bit rates are outside of the low speed standard specification limited to 100 kHz
0
0
1
0
1
0
1
0
1
but can be used with high speed TWI components limited to 400 kHz.
0.5 < ⋅ < 125
SSPE
F
PER
1
200
53.5
62.5
12.5
100
= 6 MHz
47
75
(1)
(1)
SSSTA
Bit Frequency (kHz)
0
0.67 < ⋅ < 166.7
F
PER
133.3
266.7
62.5
71.5
16.5
100
= 8 MHz
83
SSSTO
(1)
(1)
0
(1)
0.81 < ⋅ < 208.3
F
PER
104.2
166.7
333.3
SSI
78.125
125
20.83
0
= 10 MHz
89.3
(1)
(1)
(1)
(1)
(1)
SSAA
X
96 ⋅ (256 – reload value Timer 1)
F
PER
Bit Rate
SSCR1
Divided By
256
224
192
160
960
120
60
4109E–8051–06/03
PER
Bit Rate
SSCR0
) issued