AT83C51SND1C_03 ATMEL [ATMEL Corporation], AT83C51SND1C_03 Datasheet - Page 125
AT83C51SND1C_03
Manufacturer Part Number
AT83C51SND1C_03
Description
Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT83C51SND1C_03.pdf
(210 pages)
- Current page: 125 of 210
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Registers
4109E–8051–06/03
Table 112. MMCON0 Register
MMCON0 (S:E4h) – MMC Control Register 0
Reset Value = 0000 0000b
Number
DRPTR
Bit
7
7
6
5
4
3
2
1
0
Mnemonic Description
MBLOCK
CRCDIS
DTPTR
DRPTR
CRPTR
DTPTR
CTPTR
DFMT
RFMT
Bit
6
Data Receive Pointer Reset Bit
Set to reset the read pointer of the data FIFO.
Clear to release the read pointer of the data FIFO.
Data Transmit Pointer Reset Bit
Set to reset the write pointer of the data FIFO.
Clear to release the write pointer of the data FIFO.
Command Receive Pointer Reset Bit
Set to reset the read pointer of the receive command FIFO.
Clear to release the read pointer of the receive command FIFO.
Command Transmit Pointer Reset Bit
Set to reset the write pointer of the transmit command FIFO.
Clear to release the read pointer of the transmit command FIFO.
Multi-block Enable Bit
Set to select multi-block data format.
Clear to select single block data format.
Data Format Bit
Set to select the block-oriented data format.
Clear to select the stream data format.
Response Format Bit
Set to select the 48-bit response format.
Clear to select the 136-bit response format.
Clear to enable the CRC7 computation when receiving a response.
CRC7 Disable Bit
Set to disable the CRC7 computation when receiving a response.
CRPTR
5
CTPTR
4
MBLOCK
3
AT8xC51SND1C
DFMT
2
RFMT
1
CRCDIS
0
125
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