AT83C51SND1C_03 ATMEL [ATMEL Corporation], AT83C51SND1C_03 Datasheet - Page 149

• Manufacturer Part Number: AT83C51SND1C_03
• Description: Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface
• Manufacturer: ATMEL [ATMEL Corporation]

Data Transfer
Figure 115. Data Transmission Format (CPHA = 0)
4109E–8051–06/03
MOSI (From Master)
SCK Cycle Number
MISO (From Slave)
SCK (CPOL = 0)
SCK (CPOL = 1)
SPEN (Internal)
Capture point
SS (to slave)
Table 131. Serial Bit Rates
Notes:
The Clock Polarity bit (CPOL in SPCON) defines the default SCK line level in idle
state
input data are sampled and the edges on which the output data are shifted (see
Figure 115 and Figure 116). The SI signal is output from the selected slave and the SO
signal is the output from the master. The AT8xC51SND1C captures data from the SI line
while the selected slave captures data from the SO line.
For simplicity, Figure 115 and Figure 116 depict the SPI waveforms in idealized form
and do not provide precise timing information. For timing parameters refer to the Section
“AC Characteristics”.
Note:
SPR2
0
0
0
0
1
1
1
1
MSB
(1)
MSB
SPR1
1
while the Clock Phase bit (CPHA in SPCON) defines the edges on which the
1. These frequencies are achieved in X1 mode, F
2. These frequencies are achieved in X2 mode, F
1. When the peripheral is disabled (SPEN = 0), default SCK line is high level.
0
0
1
1
0
0
1
1
SPR0
bit 6
bit 6
2
0
1
0
1
0
1
0
1
6 MHz
46.875
bit 5
bit 5
187.5
93.75
3000
1500
6000
3
750
375
(1)
8 MHz
bit 4
bit 4
4
4000
2000
1000
8000
62.5
500
250
125
(1)
bit 3
bit 3
10 MHz
Bit Rate (kHz) Vs F
5
156.25
78.125
10000
312.5
5000
2500
1250
625
(1)
bit 2
bit 2
6
12 MHz
12000
187.5
93.75
6000
3000
1500
750
375
bit 1
bit 1
PER
PER
(2)
7
PER
AT8xC51SND1C
16 MHz
= F
= F
16000
8000
4000
2000
1000
500
250
125
OSC
OSC
LSB
LSB
8
(2)
.
÷ 2.
20 MHz
156.25
10000
20000
312.5
5000
2500
1250
625
(2)
F
PER
128
Divider
16
32
64
2
4
8
1
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