AT83C51SND1C_03 ATMEL [ATMEL Corporation], AT83C51SND1C_03 Datasheet - Page 129

• Manufacturer Part Number: AT83C51SND1C_03
• Description: Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface
• Manufacturer: ATMEL [ATMEL Corporation]

4109E–8051–06/03
Table 117. MMMSK Register
MMMSK (S:DFh) – MMC Interrupt Mask Register
Reset Value = 1111 1111b
Table 118. MMCMD Register
MMCMD (S:DDh) – MMC Command Register
Reset Value = 1111 1111b
Number
Number
MCBM
MC7
7 - 0
Bit
Bit
7
7
7
6
5
4
3
2
1
0
Mnemonic Description
Mnemonic Description
EORM
MCBM
EORM
EOCM
EOFM
MC7:0
F2EM
F1EM
F2FM
F1FM
MC6
Bit
Bit
6
6
MMC Card Busy Interrupt Mask Bit
Set to prevent MCBI flag from generating an MMC interrupt.
Clear to allow MCBI flag to generate an MMC interrupt.
End Of Response Interrupt Mask Bit
Set to prevent EORI flag from generating an MMC interrupt.
Clear to allow EORI flag to generate an MMC interrupt.
End Of Command Interrupt Mask Bit
Set to prevent EOCI flag from generating an MMC interrupt.
Clear to allow EOCI flag to generate an MMC interrupt.
End Of Frame Interrupt Mask Bit
Set to prevent EOFI flag from generating an MMC interrupt.
Clear to allow EOFI flag to generate an MMC interrupt.
FIFO 2 Full Interrupt Mask Bit
Set to prevent F2FI flag from generating an MMC interrupt.
Clear to allow F2FI flag to generate an MMC interrupt.
FIFO 1 Full Interrupt Mask Bit
Set to prevent F1FI flag from generating an MMC interrupt.
Clear to allow F1FI flag to generate an MMC interrupt.
FIFO 2 Empty Interrupt Mask Bit
Set to prevent F2EI flag from generating an MMC interrupt.
Clear to allow F2EI flag to generate an MMC interrupt.
FIFO 1 Empty Interrupt Mask Bit
Set to prevent F1EI flag from generating an MMC interrupt.
Clear to allow F1EI flag to generate an MMC interrupt.
MMC Command Receive Byte
Output (read) register of the response FIFO.
MMC Command Transmit Byte
Input (write) register of the command FIFO.
EOCM
MC5
5
5
EOFM
MC4
4
4
F2FM
MC3
3
3
AT8xC51SND1C
F1FM
MC2
2
2
F2EM
MC1
1
1
F1EM
MC0
0
0
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