AT83C51SND1C_03 ATMEL [ATMEL Corporation], AT83C51SND1C_03 Datasheet - Page 147

• Manufacturer Part Number: AT83C51SND1C_03
• Description: Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface
• Manufacturer: ATMEL [ATMEL Corporation]

Description
Master Mode
Figure 113. SPI Master Mode Block Diagram
Note:
4109E–8051–06/03
MSTR bit in SPCON is set to select master mode.
CLOCK
PER
MOSI/P4.1
MISO/P4.0
SCK/P4.2
SS#/P4.3
SPCON.6
SPEN
Bit Rate Generator
The SPI controller interfaces with the C51 core through three special function registers:
SPCON, the SPI control register (see Table 132); SPSTA, the SPI status register (see
Table 133); and SPDAT, the SPI data register (see Table 134).
The SPI operates in master mode when the MSTR bit in SPCON is set.
Figure 113 shows the SPI block diagram in master mode. Only a master SPI module
can initiate transmissions. Software begins the transmission by writing to SPDAT. Writ-
ing to SPDAT writes to the shift register while reading SPDAT reads an intermediate
register updated at the end of each transfer.
The Byte begins shifting out on the MOSI pin under the control of the bit rate generator.
This generator also controls the shift register of the slave peripheral through the SCK
output pin. As the Byte shifts out, another Byte shifts in from the slave peripheral on the
MISO pin. The Byte is transmitted most significant bit (MSB) first. The end of transfer is
signaled by SPIF being set.
When the AT8xC51SND1C is the only master on the bus, it can be useful not to use
SS# pin and get it back to I/O functionality. This is achieved by setting SSDIS bit in
SPCON.
SPR2:0
SPCON.5
SPCON
SSDIS
Control and Clock Logic
SPCON.2
CPHA
SPCON.3
CPOL
I
SPSTA.4
SPSTA.6
SPSTA.7
WCOL
MODF
SPIF
8-bit Shift Register
SPDAT RD
SPDAT WR
AT8xC51SND1C
Q
147