AT83C51SND1C_03 ATMEL [ATMEL Corporation], AT83C51SND1C_03 Datasheet - Page 124

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AT83C51SND1C_03

Manufacturer Part Number
AT83C51SND1C_03
Description
Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
Interrupt
Description
Figure 89. MMC Controller Interrupt System
124
AT8xC51SND1C
MMINT.7
MMINT.6
MMINT.5
MMINT.4
MMINT.3
MMINT.2
MMINT.1
MMINT.0
MCBI
EORI
EOCI
EOFI
F2EI
F1EI
F2FI
F1FI
As shown in Figure 89, the MMC controller implements eight interrupt sources reported
in MCBI, EORI, EOCI, EOFI, F2FI, F1FI, and F2EI flags in MMCINT register. These
flags are detailed in the previous sections.
All these sources are maskable separately using MCBM, EORM, EOCM, EOFM, F2FM,
F1FM, and F2EM mask bits respectively in MMMSK register.
The interrupt request is generated each time an unmasked flag is set, and the global
MMC controller interrupt enable bit is set (EMMC in IEN1 register).
Reading the MMINT register automatically clears the interrupt flags (acknowledgment).
This implies that register content must be saved and tested interrupt flag by interrupt
flag to be sure not to forget any interrupts.
MMMSK.6
MMMSK.4
MMMSK.2
MMMSK.0
EORM
EOFM
F1EM
F1FM
MMMSK.7
MMMSK.5
MMMSK.3
MMMSK.1
MCBM
EOCM
F2EM
F2FM
EMMC
IEN1.0
MMC Interface
Interrupt Request
4109E–8051–06/03

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