AT83C51SND1C_03 ATMEL [ATMEL Corporation], AT83C51SND1C_03 Datasheet - Page 142
AT83C51SND1C_03
Manufacturer Part Number
AT83C51SND1C_03
Description
Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT83C51SND1C_03.pdf
(210 pages)
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Interrupt
142
AT8xC51SND1C
SMOD0 = X
SMOD0 = 1
SMOD0 = 0
SMOD0 = 1
SMOD0 = 1
The Serial I/O Port handles 2 interrupt sources that are the “end of reception” (RI in
SCON) and “end of transmission” (TI in SCON) flags. As shown in Figure 109 these
flags are combined together to appear as a single interrupt source for the C51 core.
Flags must be cleared by software when executing the serial interrupt service routine.
The serial interrupt is enabled by setting ES bit in IEN0 register. This assumes interrupts
are globally enabled by setting EA bit in IEN0 register.
Depending on the selected mode and weather the framing error detection is enabled or
disabled, RI flag is set during the stop bit or during the ninth bit as detailed in Figure 110.
Figure 109. Serial I/O Interrupt System
Figure 110. Interrupt Waveforms
RXD
RXD
FE
FE
RI
RI
RI
Start Bit
Start bit
D0
D0
SCON.0
SCON.1
RI
TI
D1
D1
b. Mode 2 and 3
D2
D2
a. Mode 1
IEN0.4
D3
D3
ES
8-bit Data
9-bit data
D4
D4
D5
D5
Serial I/O
Interrupt Request
D6
D6
D7
D7
Stop Bit
D8
4109E–8051–06/03
Stop bit
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