AT83C51SND1C_03 ATMEL [ATMEL Corporation], AT83C51SND1C_03 Datasheet - Page 159

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AT83C51SND1C_03

Manufacturer Part Number
AT83C51SND1C_03
Description
Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
Figure 124. Complete Data Transfer on TWI Bus
4109E–8051–06/03
SDA
SCL
S
MSB
1
Slave Address
The four operating modes are:
Data transfer in each mode of operation are shown in Figure 125 through Figure 128.
These figures contain the following abbreviations:
A
A
Data
S
P
MR
MT
SLA
GCA
R
W
In Figure 125 through Figure 128, circles are used to indicate when the serial interrupt
flag is set. The numbers in the circles show the status code held in SSSTA. At these
points, a service routine must be executed to continue or complete the serial transfer.
These service routines are not critical since the serial transfer is suspended until the
serial interrupt flag is cleared by software.
When the serial interrupt routine is entered, the status code in SSSTA is used to branch
to the appropriate service routine. For each status code, the required software action
and details of the following serial transfer are given in Table 136 through Table 128.
2
Master transmitter
Master receiver
Slave transmitter
Slave receiver
Acknowledge bit (low level at SDA)
Not acknowledge bit (high level on SDA)
8-bit data Byte
START condition
STOP condition
Master Receive
Master Transmit
Slave Address
General Call Address (00h)
Read bit (high level at SDA)
Write bit (low level at SDA)
direction
R/W
bit
8
receiver
signal
ACK
from
9
Clock Line Held Low While Serial Interrupts Are Serviced
1
Nth data Byte
2
8
AT8xC51SND1C
receiver
signal
ACK
from
9
P/S
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