AT83C51SND1C_03 ATMEL [ATMEL Corporation], AT83C51SND1C_03 Datasheet - Page 153

• Manufacturer Part Number: AT83C51SND1C_03
• Description: Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface
• Manufacturer: ATMEL [ATMEL Corporation]

Master Mode with Interrupt
4109E–8051–06/03
Figure 120 shows the initialization phase and the transfer phase flows using the inter-
rupt. Using this flow prevents any overrun error occurrence.
The bit rate is selected according to Table 131.
The transfer format depends on the slave peripheral.
SS may be deasserted between transfers depending also on the slave peripheral.
Reading SPSTA at the beginning of the ISR is mandatory for clearing the SPIF flag.
Clear is effective when reading SPDAT.
Figure 120. Master SPI Interrupt Flows
program CPOL & CPHA
Select Master Mode
write data in SPDAT
SPI Initialization
Interrupt Policy
Enable interrupt
program SPR2:0
Select Bit Rate
Select Format
Start Transfer
Select Slave
Enable SPI
MSTR = 1
SPEN = 1
ESPI =1
Pn.x = L
write data in SPDAT
Start New Transfer
Service Routine
Get Data Received
Disable interrupt
Last Transfer?
Deselect Slave
SPI Interrupt
AT8xC51SND1C
Read SPSTA
Read Status
read SPDAT
SPIE = 0
Pn.x = H
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