HD6417616 RENESAS [Renesas Technology Corp], HD6417616 Datasheet - Page 190

• Manufacturer Part Number: HD6417616
• Description: 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 5 Interrupt Controller (INTC)
Table 5.5
As table 5.5 shows, between two and four on-chip peripheral modules are assigned to each
interrupt priority level setting register. Set the priority levels by setting the corresponding 4-bit
groups with values in the range of H'0 (0000) to H'F (1111). H'0 is interrupt priority level 0 (the
lowest); H'F is level 15 (the highest). When two on-chip peripheral modules are assigned to the
same bits (DMAC0 and DMAC1, or WDT and BSC refresh control unit), those two modules have
the same priority. A reset initializes IPRA–IPRE to H'0000. They are not initialized in standby
mode.
5.3.6
Vector number setting register WDT (VCRWDT) is a 16-bit read/write register that sets the WDT
interval interrupt and BSC compare match interrupt vector numbers (0–127). VCRWDT is
initialized to H'0000 by a reset. It is not initialized in standby mode.
Bits 15 and 7—Reserved: These bits are always read as 0. The write value should always be 0.
Rev. 2.00 Mar 09, 2006 page 164 of 906
REJ09B0292-0200
Register
Interrupt priority level setting
register A
Interrupt priority level setting
register B
Interrupt priority level setting
register C
Interrupt priority level setting
register D
Interrupt priority level setting
register E
Initial value:
Initial value:
Vector Number Setting Register WDT (VCRWDT)
Interrupt Request Sources and IPRA–IPRE
R/W:
R/W:
Bit:
Bit:
15
—
—
R
R
0
7
0
BCMV6 BCMV5 BCMV4 BCMV3 BCMV2 BCMV1 BCMV0
WITV6
R/W
R/W
14
Bits 15 to 12
Reserved
E-DMAC
IRQ0
TPU0
SCIF2
0
6
0
WITV5
R/W
R/W
13
0
5
0
Bits 11 to 8
DMAC0,
TPU1
DMAC1
FRT
IRQ1
SIOF
WITV4
R/W
R/W
12
0
4
0
WITV3
R/W
R/W
11
0
3
0
Bits 7 to 4
WDT, REF
IRQ2
TPU2
Reserved
SIO1
WITV2
R/W
R/W
10
0
2
0
WITV1
R/W
R/W
Bits 3 to 0
Reserved
Reserved
IRQ3
SCIF1
SIO2
9
0
1
0
WITV0
R/W
R/W
8
0
0
0