HD6417616 RENESAS [Renesas Technology Corp], HD6417616 Datasheet - Page 672

• Manufacturer Part Number: HD6417616
• Description: 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 15 Serial I/O with FIFO (SIOF)
Bit 9—Transmit Control Data Register Empty (TCD): This flag indicates when SITCDR is empty
and can be written to.
Bit 8—Receive Control Data Register Full (RCD): This flag indicates when SIRCDR is in wait
status.
Bit 7 to 4—Reserved: This bit is always read as 0. The write value should always be 0.
Bit 3—Transmit Underrun Error (TERR): Flag that indicates the occurrence of a transmit
underrun.
Rev. 2.00 Mar 09, 2006 page 646 of 906
REJ09B0292-0200
Bit 9: TCD
0
1
Bit 8: RCD
0
1
Bit 3: TERR
0
1
SITCDR transmit data is valid
TCD is cleared to 0 in the following cases:
SITCDR transmit data is invalid
TCD is set to 1 in the following cases:
Description
SIRCDR receive data is invalid
RCD is cleared to 0 in the following cases:
SIRCDR transmit data is valid
RCD is set to 1 in the following cases:
Transmission is in progress, or has ended normally
[Clearing conditions]
A transmit underrun error has occurred
Description
Description
When 0 is written to TCD after reading TCD = 1
After data is transferred from SITCDR to SITSR
When the processor is reset
When 0 is written to RCD after reading RCD = 1
When the processor is reset
After control data has been received normally and data has been
transferred from SIRSR to SIRCDR
When 0 is written to the TERR bit after reading TERR = 1
When the TFRST bit in SIFCR is set to 1
When the processor enters the reset state
When the amount of primary transmit data in SITDR is 0 and data is
transferred from SITDR to SITSR using a transmit operation
(Initial value)
(Initial value)
(Initial value)