HD6417616 RENESAS [Renesas Technology Corp], HD6417616 Datasheet - Page 507

• Manufacturer Part Number: HD6417616
• Description: 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 11.5 Selecting the External Request Signal with the DS and DL Bits
On-Chip Module Request Mode: In this mode, transfers are started by a transfer request signal
(interrupt request signal) from an on-chip peripheral module. Transfer request signals include
SCIF, SIOF or SIO receive-data-full interrupts (RXI, RDFI), SCIF, SIOF or SIO transmit-data-
empty interrupts (TXI, TDEI), and TPU general registers (table 11.6). If DMA transfer is enabled
(DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), DMA transfer starts upon input of a transfer
request signal.
When RXI or RDFI (transfer request due to an SCIF, SIOF or SIO receive-data-full condition) is
set as a transfer request, the transfer source must be the receive data register of the corresponding
module (SCFRDR or SIRDR). When TXI or TDEI (transfer request due to an SCIF, SIOF or SIO
transmit-data-empty condition) is set as a transfer request, the transfer destination must be the
transmit data register of the corresponding module (SCFTDR or SITDR).
These restrictions do not apply to TPU transfer requests.
When on-chip module request mode is used, an access size permitted by the peripheral module
register used as the transfer source or transfer destination must be set in bits TS1 and TS0 of
CHCR0 and CHCR1.
DS
0
1
CHCR
DL
0
1
0
1
External Request
Low-level detection (can only be set in cycle-steal mode)
High-level detection (can only be set in cycle-steal mode)
Falling-edge detection
Rising-edge detection
Section 11 Direct Memory Access Controller (DMAC)
Rev. 2.00 Mar 09, 2006 page 481 of 906
REJ09B0292-0200