HD6417616 RENESAS [Renesas Technology Corp], HD6417616 Datasheet - Page 352

• Manufacturer Part Number: HD6417616
• Description: 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 Bus State Controller (BSC)
7.6.3
The basic timing of a DRAM access is 3 cycles. Figure 7.40 shows the basic DRAM access
timing. Tp is the precharge cycle, Tr is the RAS assert cycle, Tc1 is the CAS assert cycle, and Tc2
is the read data fetch cycle. When accesses are consecutive, the Tp cycle of the next access
overlaps the Tc2 cycle of the previous access, so accesses can be performed in a minimum of 3
cycles each.
Rev. 2.00 Mar 09, 2006 page 326 of 906
REJ09B0292-0200
Basic Timing
Read
Write
Note: * DACKn waveform when active-low is specified.
CKIO
A24–A16
A15–A1
RAS
CASn
RD/WR
RD
D31–D0
RD/WR
RD
D31–D0
DACKn*
Figure 7.40 Basic Access Timing
Tp
Tr
Tc1
Tc2