HD6417616 RENESAS [Renesas Technology Corp], HD6417616 Datasheet - Page 78

• Manufacturer Part Number: HD6417616
• Description: 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 2 CPU
2.4
2.4.1
The addressing modes and effective address calculation for instructions executed by the CPU core
are listed in table 2.12.
Table 2.12 CPU Instruction Addressing Modes and Effective Addresses
Rev. 2.00 Mar 09, 2006 page 52 of 906
REJ09B0292-0200
Addressing
Mode
Direct register
addressing
Indirect register
addressing
Post-increment
indirect register
addressing
Pre-decrement
indirect register
addressing
Instruction Formats
CPU Instruction Addressing Modes
Instruction
Format
Rn
@Rn
@Rn+
@–Rn
Effective Addresses Calculation
The effective address is register Rn
(The operand is the contents of register Rn)
The effective address is the content of register
Rn
The effective address is the content of register
Rn. A constant is added to the content of Rn after
the instruction is executed. 1 is added for a byte
operation, 2 for a word operation, and 4 for a
longword operation
The effective address is the value obtained by
subtracting a constant from Rn. 1 is subtracted
for a byte operation, 2 for a word operation, and
4 for a longword operation
1/2/4
1/2/4
Rn
Rn
Rn
Rn + 1/2/4
Rn – 1/2/4
+
–
Rn – 1/2/4
Rn
Rn
Equation
—
Rn
Rn
(After the
instruction
executes)
Byte: Rn + 1
Word: Rn + 2
Longword: Rn + 4
Byte: Rn – 1
Word: Rn – 2
Rn
Longword: Rn – 4
executed with Rn
after calculation)
Rn
Rn (Instruction
Rn
Rn
Rn