HD6417616 RENESAS [Renesas Technology Corp], HD6417616 Datasheet - Page 634

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HD6417616

Manufacturer Part Number
HD6417616
Description
32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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Section 14 Serial Communication Interface with FIFO (SCIF)
In serial transmission, the SCIF operates as described below.
1. When data is written to SCFTDR, the SCIF transfers the data to SCTSR and starts
2. When data is transferred from SCFTDR to SCTSR and transmission is started, transmit
3. The SCIF checks for transmit data in SCFTDR at the timing for sending the stop bit. If there is
Rev. 2.00 Mar 09, 2006 page 608 of 906
REJ09B0292-0200
transmitting. Check that the TDFE flag is set to 1 in SC1SSR before writing transmit data to
SCFTDR. The number of data bytes that can be written is at least {16 – (transmit trigger set
number)}.
operations are performed continually until there is no transmit data left in SCFTDR. If the
number of data bytes in SCFTDR falls to or below the transmit trigger number set in SCFCR
during transmission, the TDFE flag is set to 1. If the TIE bit setting in SCSCR is 1 at this time,
a transmit-FIFO-data-empty interrupt (TXI) is requested.
The serial transmit data is sent from the TxD pin in the following order.
a. Start bit: One 0-bit is output.
b. Transmit data: 8-bit or 7-bit data is output in LSB-first or MSB-first order according to the
c. Multiprocessor bit: One multiprocessor bit (MPBT value) is output.
d. Stop bit(s): One or two 1-bits (stop bits) are output.
e. Mark state: 1 is output continuously until the start bit that starts the next transmission is
data in SCFTDR, it is transferred to SCTSR, the stop bit is sent, and then serial transmission of
the next frame is started.
If there is no transmit data in SCFTDR, the TEND flag is set to 1 in SC1SSR, the stop bit is
sent, and then the line goes to the mark state in which 1 is output continuously.
Figure 14.13 shows an example of SCIF operation for transmission using a multiprocessor
format.
setting of the TLM bit in SC2SSR.
sent.

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