HD6417616 RENESAS [Renesas Technology Corp], HD6417616 Datasheet - Page 458

• Manufacturer Part Number: HD6417616
• Description: 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC)
10.2.7
EESIPR enables interrupts corresponding to individual bits in the EtherC/E-DMAC status register.
An interrupt is enabled by writing 1 to the corresponding bit. In the initial state, interrupts are not
enabled.
Bits 31 to 25—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 24—Receive Frame Counter Overflow Interrupt Permission (RFCOFIP): Enables the receive
frame counter overflow interrupt.
Bit 24: RFCOFIP Description
0
1
Rev. 2.00 Mar 09, 2006 page 432 of 906
REJ09B0292-0200
Initial value:
Initial value:
Initial value:
Initial value:
EtherC/E-DMAC Status Interrupt Permission Register (EESIPR)
R/W:
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
Bit:
RMAFIP
Receive frame counter overflow interrupt is disabled
Receive frame counter overflow interrupt is enabled
R/W
31
23
15
—
—
—
R
R
R
0
0
0
7
0
ECIIP
R/W
30
22
14
—
—
—
R
R
R
0
0
0
6
0
RFARIP
TCIP
R/W
R/W
29
21
13
—
—
R
R
0
0
0
5
0
TDEIP
RRFIP
ITFIP
R/W
R/W
R/W
28
20
12
—
R
0
0
0
4
0
TFUFIP
RTLFIP RTSFIP
CNDIP
R/W
R/W
R/W
27
19
11
—
R
0
0
0
3
0
DLCIP
FRIP
R/W
R/W
R/W
26
18
10
—
R
0
0
0
2
0
RDEIP
PREIP
CDIP
R/W
R/W
R/W
25
17
—
R
0
0
9
0
1
0
(Initial value)
RFCOFIP
CERFIP
RFOFIP
TROIP
R/W
R/W
R/W
R/W
24
16
0
0
8
0
0
0