HD6417616 RENESAS [Renesas Technology Corp], HD6417616 Datasheet - Page 591

• Manufacturer Part Number: HD6417616
• Description: 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Bit 5—Parity Enable (PE)/IrDA Clock Select 2 (ICK2): In asynchronous mode, selects whether or
not parity bit addition is performed in transmission, and parity bit checking in reception. In
synchronous mode, parity bit addition and checking is not performed, regardless of the PE bit
setting.
Bit 5: PE
0
1
Note: * When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to
In IrDA communication mode, bit 5 is the IrDA clock select 2 (ICK2) bit, enabling appropriate
clock pulses to be generated according to its setting. See Pulse Width Selection, in section 14.3.6,
Operation in IrDA Mode, for details.
Bit 4—Parity Mode (O/E)/IrDA Clock Select 1 (ICK1): Selects either even or odd parity for use in
parity addition and checking. The O/E bit setting is only valid when the PE bit is set to 1, enabling
parity bit addition and checking, in asynchronous mode. The O/E bit setting is invalid in
synchronous mode, and when parity addition and checking is disabled in asynchronous mode.
Bit 4: O/E E E E
0
1
Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total
In IrDA communication mode, bit 4 is the IrDA clock select 1 (ICK1) bit, enabling appropriate
clock pulses to be generated according to its setting. See Pulse Width Selection, in section 14.3.6,
Operation in IrDA Mode, for details.
transmit data before transmission. In reception, the parity bit is checked for the parity (even
or odd) specified by the O/E bit.
2. When odd parity is set, parity bit addition is performed in transmission so that the total
number of 1-bits in the transmit character plus the parity bit is even. In reception, a
check is performed to see if the total number of 1-bits in the receive character plus the
parity bit is even.
number of 1-bits in the transmit character plus the parity bit is odd. In reception, a check
is performed to see if the total number of 1-bits in the receive character plus the parity
bit is odd.
Parity bit addition and checking disabled
Parity bit addition and checking enabled *
Description
Even parity *
Odd parity *
Description
2
1
Section 14 Serial Communication Interface with FIFO (SCIF)
Rev. 2.00 Mar 09, 2006 page 565 of 906
REJ09B0292-0200
(Initial value)
(Initial value)