HD6417616 RENESAS [Renesas Technology Corp], HD6417616 Datasheet - Page 222

• Manufacturer Part Number: HD6417616
• Description: 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 5 Interrupt Controller (INTC)
Rev. 2.00 Mar 09, 2006 page 196 of 906
REJ09B0292-0200
Figure 5.12 Pipeline Operation when Interrupts are Enabled by Means of SR Modification
Synchronization instruction
RTE instruction
Delay slot instruction
Interrupt return destination instruction
IRL3–IRL0
F: Instruction fetch ............... Instruction is fetched from memory in which program is stored
D: Instruction decode ........... Fetched instruction is decoded
E: Instruction execution ........ Data operation or address operation is performed in accordance
M: Memory access ................ Memory data access is performed
W: Write-back ....................... Data read from memory is written to register
Interrupt clear instruction
Synchronization instruction
LDC instruction
Interrupt disable instruction
Normal instruction
IRL3–IRL0
Interrupt clear instruction
When an interrupt source is cleared by the program, pipeline operation must be considered
to ensure that the same interrupt is not implemented again.
Figure 5.11 Pipeline Operation when Returning by Means of RTE Instruction
•
•
•
D
D
with result of decoding
E
D
E
D
M
E
D
Write completed
M
E
Write completed
M
M
External write
cycle
0.5Icyc + 1.0Ecyc + 1.5Pcyc
External write
cycle
0.5Icyc + 1.0Ecyc + 1.5Pcyc
E
W
M
Next interrupt can be accepted
W
Next interrupt can be accepted
External read
cycle
M
External read
cycle
D
D
F
E
D
E
D
D
E
E
E