HD6417616 RENESAS [Renesas Technology Corp], HD6417616 Datasheet - Page 574

• Manufacturer Part Number: HD6417616
• Description: 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 13 Watchdog Timer (WDT)
of writing to RSTCSR differs from that of most other registers to prevent inadvertent rewriting.
See section 13.2.4, Notes on Register Access, for details. RSTCR is initialized to H'1D by input of
a reset signal from the RES pin, but is not initialized by the internal reset signal generated by
overflow of the WDT. It is initialized to H'1D in standby mode, when the clock frequency is
changed, and in clock pause mode.
Bit 7—Watchdog Timer Overflow Flag (WOVF): Indicates that WTCNT has overflowed (from
H'FF to H'00) in watchdog timer mode. It is not set in interval timer mode.
Bit 6—Reset Enable (RSTE): Selects whether to reset the chip internally if WTCNT overflows in
watchdog timer mode.
Bit 5—Reset Select (RSTS): Selects the type of internal reset generated if WTCNT overflows in
watchdog timer mode.
Bits 4 to 2, bit 0—Reserved: These bits are always read as 1. The write value should always be 1.
Bit 1— Reserved: This bit is always read as 0. The write value should always be 0.
Rev. 2.00 Mar 09, 2006 page 548 of 906
REJ09B0292-0200
Bit 7: WOVF
0
1
Bit 6: RSTE
0
1
Bit 5: RSTS
0
1
Description
No WTCNT overflow in watchdog timer mode
Cleared by reading WOVF, then writing 0 in WOVF
Set by WTCNT overflow in watchdog timer mode
Description
Not reset when WTCNT overflows
LSI not reset internally, but WTCNT and WTCSR reset within WDT
Reset when WTCNT overflows
Description
Power-on reset
Manual reset
(Initial value)
(Initial value)
(Initial value)