HD6417616 RENESAS [Renesas Technology Corp], HD6417616 Datasheet - Page 550

• Manufacturer Part Number: HD6417616
• Description: 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 16-Bit Free-Running Timer (FRT)
Bits 6 to 4—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 3—Output Compare Interrupt A Enable (OCIAE): Selects enabling/disabling of the OCIA
interrupt request when the output compare flag A (OCFA) in FTCSR is set to 1.
Bit 3: OCIAE
0
1
Bit 2—Output Compare Interrupt B Enable (OCIBE): Selects enabling/disabling of the OCIB
interrupt request when the output compare flag B (OCFB) in FTCSR is set to 1.
Bit 2: OCIBE
0
1
Bit 1—Timer Overflow Interrupt Enable (OVIE): Selects enabling/disabling of the OVI interrupt
request when the overflow flag (OVF) in FTCSR is set to 1.
Bit 1: OVIE
0
1
Bit 0—Reserved: This bit is always read as 1. The write value should always be 1.
12.2.5
Note: * For bits 7, and 3 to 1, the only value that can be written is 0 (to clear the flags).
FTCSR is an 8-bit register that selects counter clearing and controls interrupt request signals.
FTCSR is initialized to H'00 by a reset, in standby mode, and when the module standby function is
used. See section 12.4, Operation, for the timing.
Rev. 2.00 Mar 09, 2006 page 524 of 906
REJ09B0292-0200
Initial value:
Free-Running Timer Control/Status Register (FTCSR)
R/W:
Bit:
R/(W) *
ICF
7
0
Description
Interrupt request (OCIA) caused by OCFA disabled
Interrupt request (OCIA) caused by OCFA enabled
Description
Interrupt request (OCIB) caused by OCFB disabled
Interrupt request (OCIB) caused by OCFB enabled
Description
Interrupt request (OVI) caused by OVF disabled
Interrupt request (OVI) caused by OVF enabled
—
R
6
0
—
R
5
0
—
R
4
0
R/(W) *
OCFA
3
0
R/(W) *
OCFB
2
0
R/(W) *
OVF
1
0
(Initial value)
(Initial value)
(initial value)
CCLRA
R/W
0
0