HD6417616 RENESAS [Renesas Technology Corp], HD6417616 Datasheet - Page 379

• Manufacturer Part Number: HD6417616
• Description: 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

7.10.4
The BUSHiZ pin is needed when the SH7616 is connected to a PCI controller via a PCI bridge,
and the PCI master and SH7616 share local memory on the SH7616 bus. By using this pin in
combination with the WAIT pin, it is possible to place the bus and specific control signals in the
high-impedance state while keeping the SH7616's internal state halted. The conditions for
establishing the high-impedance state, the applicable pins, and the bus timing (figure 7.60) are
shown below. See the Application Note for an example of PCI bridge connection.
CKIO
WAIT
BUSHiZ
Target pins
1. Can be used when memory is shared by the CPU and an external device.
2. When BUSHiZ is asserted after asserting WAIT, the CPU appears to release the bus.
3. When it becomes possible to access the shared memory, BUSHiZ is negated.
4. When the data is ready, WAIT is negated.
This procedure allows the CPU and an external device to share memory.
CKIO
Address
CSn
STATS1, 0
Note: In on-chip I/O
High-impedance conditions: Not dependent on BCR settings etc. when WAIT = L and
BUSHiZ = L
Applicable pins: A[24:0], D[31:0], CS3, RD/WR, RD, RAS, CAS/OE, DQMLL/WE0,
DQMLU/WE1, DQMUL/WE2, DQMUU/WE3 (total of 66 pins)
accesses to on-chip I/O and on-chip RAM are included in the “Others” category.
BUSHiZ
BUSHiZ
BUSHiZ
BUSHiZ Specification
CPU
on-chip RAM or on-chip I/O
00
CPU
Figure 7.59 STATS Output Timing
Figure 7.60 BUSHiZ
E-DMAC E-DMAC
BUSHiZ
BUSHiZ Bus Timing
BUSHiZ
memory transfers using the DMAC,
10
E-DMAC
Rev. 2.00 Mar 09, 2006 page 353 of 906
Period
Section 7 Bus State Controller (BSC)
E-DMAC G-DMAC G-DMAC G-DMAC
REJ09B0292-0200
01